Renesas ZTAT H8S/2357F, Руководство по оборудованию

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Rev.6.00 Oct.28.2004 page 57 of 1016
REJ09B0138-0600H
3.1.3 Register Configuration
The H8S/2357 Group has a mode control register (MDCR) that indicates the inputs at the mode pins (MD
2
to MD
0
), and a
system control register (SYSCR) and a system control register 2 (SYSCR2)*
2
that control the operation of the H8S/2357
Group. Table 3-3 summarizes these registers.
Table 3-3 MCU Registers
Name Abbreviation R/W Initial Value Address *
1
Mode control register MDCR R Undetermined H'FF3B
System control register SYSCR R/W H'01 H'FF39
System control register 2 *
2
SYSCR2 R/W H'00 H'FF42
Notes: 1. Lower 16 bits of the address.
2. The SYSCR2 register can only be used in the F-ZTAT version. In the masked ROM and ZTAT versions, this
register cannot be written to and will return an undefined value if read.
3.2 Register Descriptions
3.2.1 Mode Control Register (MDCR)
Bit : 7 6 5 4 3 2 1 0
— — — — — MDS2 MDS1 MDS0
Initial value : 1 0 0 0 0 — * — * — *
R/W : — — — — — R R R
Note: * Determined by pins MD
2
to MD
0
.
MDCR is an 8-bit read-only register that indicates the current operating mode of the H8S/2357 Group.
Bit 7—Reserved: This bit cannot be modified and is always read as 1.
Bits 6 to 3—Reserved: These bits cannot be modified and are always read as 0.
Bits 2 to 0—Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the input levels at pins MD
2
to MD
0
(the current
operating mode). Bits MDS2 to MDS0 correspond to MD
2
to MD
0
. MDS2 to MDS0 are read-only bits, they cannot be
written to. The mode pin (MD
2
to MD
0
) input levels are latched into these bits when MDCR is read. These latches are
canceled by a power-on reset, but are retained after a manual reset.*
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
3.2.2 System Control Register (SYSCR)
Bit : 7 6 5 4 3 2 1 0
— — INTM1 INTM0 NMIEG — — RAME
Initial value : 0 0 0 0 0 0 0 1
R/W : R/W — R/W R/W R/W —
*
R/W R/W
Note:
*
R/W in the H8S/2390, H8S/2392, H8S/2394, and H8S/2398.