Renesas ZTAT H8S/2357F, Руководство по оборудованию

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Rev.6.00 Oct.28.2004 page 17 of 1016
REJ09B0138-0600H
Pin No.
Type Symbol TFP-120 FP-128B I/O Name and Function
Address bus A
23
to
A
0
28 to 25,
23 to 16,
14 to 7,
5 to 2 32 to 29,
27 to 20,
18 to 11,
9 to 6 Output Address bus: These pins output an
address.
Data bus D
15
to
D
0
51 to 48,
46 to 39,
37 to 34 57 to 54,
52 to 45,
43 to 40 I/O Data bus: These pins constitute a
bidirectional data bus.
Bus control
CS7
to
CS0
120 to 117
61, 60,
30, 29 128, 127,
69, 66,
34, 33,
2, 1 Output Chip select: Signals for selecting
areas 7 to 0.
AS
82 90 Output Address strobe: When this pin is
low, it indicates that address output
on the address bus is enabled.
RD
83 91 Output Read: When this pin is low, it
indicates that the external address
space can be read.
HWR
84 92 Output High write/write enable:
A strobe signal that writes to external
space and indicates that the upper
half (D
15
to D
8
) of the data bus is
enabled.
The 2CAS type DRAM write enable
signal.
LWR
85 93 Output Low write:
A strobe signal that writes to external
space and indicates that the lower
half (D
7
to D
0
) of the data bus is
enabled.
CAS
116 126 Output Upper column address
strobe/column address strobe:
The 2CAS type DRAM upper column
address strobe signal.
WAIT
86 94 Input Wait: Requests insertion of a wait
state in the bus cycle when
accessing external 3-state address
space.
LCAS
86 94 Output Lower column address strobe: The
2-CAS type DRAM lower column
address strobe signal
DMA controller
(DMAC)
DREQ1,
DREQ0
62, 60 70, 66 Input DMA request 1 and 0: These pins
request DMAC activation.
TEND1
,
TEND0
63, 61 71, 69 Output DMA transfer end 1 and 0: These
pins indicate the end of DMAC data
transfer.
DACK1
,
DACK0
112, 111 122, 121 Output DMA transfer acknowledge 1 and
0: These are the DMAC single
address transfer acknowledge pins.