Renesas ZTAT H8S/2357F, Руководство по оборудованию

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Rev.6.00 Oct.28.2004 page 581 of 1016
REJ09B0138-0600H
19.6.4 Pin Configuration
The flash memory is controlled by means of the pins shown in table 19-10.
Table 19-10 Flash Memory Pins
Pin Name Abbreviation I/O Function
Reset
RES
Input Reset
Flash write enable FWE Input Flash program/erase protection by hardware
Mode 2 MD
2
Input Sets MCU operating mode
Mode 1 MD
1
Input Sets MCU operating mode
Mode 0 MD
0
Input Sets MCU operating mode
Port 66 P66 Input Sets MCU operating mode in programmer
mode
Port 65 P65 Input Sets MCU operating mode in programmer
mode
Port 64 P64 Input Sets MCU operating mode in programmer
mode
Transmit data TxD1 Output Serial transmit data output
Receive data RxD1 Input Serial receive data input
19.6.5 Register Configuration
The registers used to control the on-chip flash memory when enabled are shown in table 19-11.
In order for these registers to be accessed, the FLSHE bit must be set to 1 in SYSCR2 (except RAMER).
Table 19-11 Flash Memory Registers
Register Name Abbreviation R/W Initial Value Address
*
1
Flash memory control register 1 FLMCR1
*
6
R/W
*
3
H'00
*
4
H'FFC8
*
2
Flash memory control register 2 FLMCR2
*
6
R/W
*
3
H'00
*
5
H'FFC9
*
2
Erase block register 1 EBR1
*
6
R/W
*
3
H'00
*
5
H'FFCA
*
2
Erase block register 2 EBR2
*
6
R/W
*
3
H'00
*
5
H'FFCB
*
2
System control register 2 SYSCR2
*
7
R/W H'00 H'FF42
RAM emulation register RAMER R/W H'00 H'FEDB
Notes: 1. Lower 16 bits of the address.
2. Flash memory registers are selected by the FLSHE bit in system control register 2 (SYSCR2).
3. In modes in which the on-chip flash memory is disabled, a read will return H'00, and writes are invalid. Writes
are also disabled when the FWE bit is cleared to 0 in FLMCR1.
4. When a high level is input to the FWE pin, the initial value is H'80.
5. When a low level is input to the FWE pin, or if a high level is input and the SWE bit in FLMCR1 is not set, these
registers are initialized to H'00.
6. FLMCR1, FLMCR2, EBR1, and EBR2 are 8-bit registers. Only byte accesses are valid for these registers, the
access requiring 2 states.
7. SYSCR2 is available only in the F-ZTAT version. In the masked ROM and ZTAT versions, this register cannot
be written to and will return an undefined value if read.