Renesas ZTAT H8S/2357F, Руководство по оборудованию

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Rev.6.00 Oct.28.2004 page 549 of 1016
REJ09B0138-0600H
16.4.3 Input Sampling and A/D Conversion Time
The A/D converter has a on-chip sample-and-hold circuit. The A/D converter samples the analog input at a time t
D
after
the ADST bit is set to 1, then starts conversion. Figure 16-5 shows the A/D conversion timing. Table 16-4 indicates the
A/D conversion time.
As indicated in figure 16-5, the A/D conversion time includes t
D
and the input sampling time. The length of t
D
varies
depending on the timing of the write access to ADCSR. The total conversion time therefore varies within the ranges
indicated in table 16-4.
In scan mode, the values given in table 16-4 apply to the first conversion time. In the second and subsequent conversions
the conversion time is fixed at 256 states when CKS = 0 or 128 states when CKS = 1.
(1)
(2)
t
D
t
SPL
t
CONV
ø
Input sampling
timing
ADF
Address bus
Write signal
Legend:
(1):
ADCSR write cycle
(2): ADCSR address
t
D:
A/D conversion start delay
t
SPL:
Input sampling time
t
CONV:
A/D conversion time
Figure 16-5 A/D Conversion Timing
Table 16-4 A/D Conversion Time (Single Mode)
CKS = 0 CKS = 1
Item Symbol Min Typ Max Min Typ Max
A/D conversion start delay t
D
10 — 17 6 — 9
Input sampling time t
SPL
— 63 — — 31 —
A/D conversion time t
CONV
259 — 266 131 — 134
Note: Values in the table are the number of states.