Renesas RZ/G1M, Руководство пользователя

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RZ/G1M 5. Pin Function Controller (PFC)
R01UH0626EJ0100 Rev.1.00 5-30
Sep 30,2016
5.3.17 Peripheral Function Select Register 7 (IPSR7)
Function: IPSR7 selects the functions of the multiplexed LSI pins.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
— —
IP7
[29]
IP7
[28]
IP7
[27]
IP7
[26]
IP7
[25]
IP7
[24]
IP7
[23]
IP7
[22]
IP7
[21]
IP7
[20]
IP7
[19]
IP7
[18]
IP7
[17]
IP7
[16]
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IP7
[15]
IP7
[14]
IP7
[13]
IP7
[12]
IP7
[11]
IP7
[10]
IP7
[9]
IP7
[8]
IP7
[7]
IP7
[6]
IP7
[5]
IP7
[4]
IP7
[3]
IP7
[2]
IP7
[1]
IP7
[0]
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit Initial Value R/W Description
31 to 0 H'0000 0000 R/W The functions of the LSI pins are selected according to the table below.
Note: To enable this register to be set, appropriately set the multiplexed pin setting mask register (PMMR) immediately
before setting this register.
Bit
Name
Function 1
(Set Value
= H'0)
Function 2
(Set Value
= H'1)
Function 3
(Set Value
= H'2)
Function 4
(Set Value
= H'3)
Function 5
(Set Value
= H'4)
Function 6
(Set Value
= H'5)
Others
(Set Value =
H'6 to H'F)
IP7[2:0] IRQ9 DU1_DOTCLKIN_B CAN_CLK_D — SCIF_CLK_B — —
IP7[5:3] DU1_DR0 — VI1_DATA0_B TX0_B SCIFA0_TXD_B MSIOF2_SCK_B —
IP7[8:6] DU1_DR1 — VI1_DATA1_B RX0_B SCIFA0_RXD_B MSIOF2_SYNC_B —
IP7[10:9] DU1_DR2 — SSI_SCK0129_B — — — —
IP7[12:11] DU1_DR3 — SSI_WS0129_B — — — —
IP7[14:13] DU1_DR4 — SSI_SDATA0_B — — — —
IP7[16:15] DU1_DR5 — SSI_SCK1_B — — — —
IP7[18:17] DU1_DR6 — SSI_WS1_B — — — —
IP7[20:19] DU1_DR7 — SSI_SDATA1_B — — — —
IP7[23:21] DU1_DG0 — VI1_DATA2_B TX1_B SCIFA1_TXD_B MSIOF2_SS1_B —
IP7[26:24] DU1_DG1 — VI1_DATA3_B RX1_B SCIFA1_RXD_B MSIOF2_SS2_B —
IP7[29:27] DU1_DG2 — VI1_DATA4_B SCIF1_SCK_B SCIFA1_SCK SSI_SCK78_B —
Legend:
—
Setting prohibited