Renesas RZ/G1M, Руководство пользователя

Страница: 119 / 184

RZ/G1M 5. Pin Function Controller (PFC)
R01UH0626EJ0100 Rev.1.00 5-28
Sep 30,2016
5.3.15 Peripheral Function Select Register 5 (IPSR5)
Function: IPSR5 selects the functions of the multiplexed LSI pins.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IP5
[31]
IP5
[30]
IP5
[29]
IP5
[28]
IP5
[27]
IP5
[26]
IP5
[25]
IP5
[24]
IP5
[23]
IP5
[22]
IP5
[21]
IP5
[20]
IP5
[19]
IP5
[18]
IP5
[17]
IP5
[16]
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IP5
[15]
IP5
[14]
IP5
[13]
IP5
[12]
IP5
[11]
IP5
[10]
IP5
[9]
IP5
[8]
IP5
[7]
IP5
[6]
IP5
[5]
IP5
[4]
IP5
[3]
IP5
[2]
IP5
[1]
IP5
[0]
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit Initial Value R/W Description
31 to 0 H'0000 0000 R/W The functions of the LSI pins are selected according to the table below.
Note: To enable this register to be set, appropriately set the multiplexed pin setting mask register (PMMR) immediately
before setting this register.
Bit Name
Function 1
(Set Value
= H'0)
Function 2
(Set Value
= H'1)
Function 3
(Set Value
= H'2)
Function 4
(Set Value
= H'3)
Function 5
(Set Value
= H'4)
Function 6
(Set Value
= H'5)
Function 7
(Set Value
= H'6)
Others
(Set Value =
H'7 to H'F)
IP5[2:0] SSI_WS5 MSIOF1_SYNC_C TS_SCK0 — MSIOF2_TXD_D VI1_R3_B — —
IP5[5:3] SSI_SDATA5 MSIOF1_TXD_C TS_SDEN0 — MSIOF2_SS1_D VI1_R4_B — —
IP5[8:6] SSI_SCK6 MSIOF1_RXD_C TS_SPSYNC0 — MSIOF2_RXD_D VI1_R5_B — —
IP5[11:9] SSI_WS6 — MSIOF2_SS2_D VI1_R6_B — — — —
IP5[14:12] SSI_SDATA6 — — VI1_R7_B — — — —
IP5[16:15] SSI_SCK78 — — — — — — —
IP5[19:17] SSI_WS78 TX0_D — — — — — —
IP5[21:20] SSI_SDATA7 RX0_D — — — — — —
IP5[23:22] SSI_SDATA8 TX1_D — — — — — —
IP5[25:24] SSI_SCK9 RX1_D — — — — — —
IP5[28:26] SSI_WS9 TX3_D CAN0_TX_D — — — — —
IP5[31:29] SSI_SDATA9 RX3_D CAN0_RX_D — — — — —
Legend:
—
Setting prohibited