Renesas RZ/G1M, Руководство пользователя

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RZ/G1M 5. Pin Function Controller (PFC)
R01UH0626EJ0100 Rev.1.00 5-80
Sep 30,2016
5.3.45 DDR3 General Port IO Enable Register (DDR3GPEN)
Function: DDR3GPEN is used to write values to enable DDR3 general port function.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DDR3EN[31:16]
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DDR3EN[15:0]
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit Bit Name
Initial
Value R/W
Description
31, 30 DDR3EN[31:30] 00 R/W —
29 to 1 DDR3EN[29:1] 0 R/W For enabling DDR3 general port function bit 29 to 1:
0: Disabled.
1: Enabled.
0 DDR3EN[0] 0 R/W —
Note: To enable this register to be set, appropriately set the multiplexed pin setting mask register (PMMR) immediately
before setting this register.