Renesas RZ/G1M, Руководство пользователя

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RZ/G1M 5. Pin Function Controller (PFC)
R01UH0626EJ0100 Rev.1.00 5-75
Sep 30,2016
5.3.41 TDSEL Control Register 4 (IOCTRL4)
Function: IOCTRL4 controls the delay of returned clock of in pins of IRQ, DU and Ethernet interfaces.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
— — — — — — — — — — — — — — — —
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
— —
irq5_tds
el1
irq5_tds
el0
du1dr0
_tdsel1
du1dr0
_tdsel0
— — — — — —
ethlink_
tdsel1
ethlink_
tdsel0
stpisclk
_tdsel1 stpisclk
_tdsel0
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit Bit Name
Initial
Value R/W Description
31 to 14 — All 0 R/W —
13 irq5_tdsel1 0 R/W IRQ5 Setting:
The value of these bits must be 00. 12 irq5_tdsel0 0 R/W
11 du1dr0_tdsel1 0 R/W DU1_DR0 Setting:
The value of these bits must be 00.
10 du1dr0_tdsel0 0 R/W
9 to 4 — All 0 R/W —
3 ethlink_tdsel1 0 R/W ETH_LINK Setting:
The value of these bits must be 00.
2 ethlink_tdsel0 0 R/W
1 stpisclk_tdsel1 0 R/W STP_ISCLK_0 Setting:
The value of these bits must be 00.
0 stpisclk_tdsel0 0 R/W
Note: To enable this register to be set, appropriately set the multiplexed pin setting mask register (PMMR) immediately
before setting this register.