Renesas RZ/G1M, Руководство пользователя

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RZ/G1M 5. Pin Function Controller (PFC)
R01UH0626EJ0100 Rev.1.00 5-35
Sep 30,2016
5.3.22 Peripheral Function Select Register 12 (IPSR12)
Function: IPSR12 selects the functions of the multiplexed LSI pins.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
— —
IP12
[29]
IP12
[28]
IP12
[27]
IP12
[26]
IP12
[25]
IP12
[24]
IP12
[23]
IP12
[22]
IP12
[21]
IP12
[20]
IP12
[19]
IP12
[18]
IP12
[17]
IP12
[16]
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IP12
[15]
IP12
[14]
IP12
[13]
IP12
[12]
IP12
[11]
IP12
[10]
IP12
[9]
IP12
[8]
IP12
[7]
IP12
[6]
IP12
[5]
IP12
[4]
IP12
[3]
IP12
[2]
IP12
[1]
IP12
[0]
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit Initial Value R/W Description
31 to 0 H'0000 0000 R/W The functions of the LSI pins are selected according to the table below.
Note: To enable this register to be set, appropriately set the multiplexed pin setting mask register (PMMR) immediately
before setting this register.
Bit Name
Function 1
(Set Value
= H'0)
Function 2
(Set Value
= H'1)
Function 3
(Set Value
= H'2)
Function 4
(Set Value
= H'3)
Function 5
(Set Value
= H'4)
Others
(Set Value =
H'5 to H'F)
IP12[1:0] ETH_RX_ER AVB_CRS I2C3_SCL IIC0_SCL — —
IP12[3:2] ETH_RXD0 AVB_PHY_INT I2C3_SDA IIC0_SDA — —
IP12[6:4] ETH_RXD1 AVB_GTXREFCLK CAN0_TX_C I2C2_SCL_D MSIOF1_RXD_E —
IP12[9:7] ETH_LINK AVB_TXD0 CAN0_RX_C I2C2_SDA_D MSIOF1_SCK_E —
IP12[12:10] ETH_REFCLK AVB_TXD1 SCIFA3_RXD_B CAN1_RX_C MSIOF1_SYNC_E —
IP12[15:13] ETH_TXD1 AVB_TXD2 SCIFA3_TXD_B CAN1_TX_C MSIOF1_TXD_E —
IP12[17:16] ETH_TX_EN AVB_TXD3 TCLK1_B CAN_CLK_B — —
IP12[19:18] ETH_MAGIC AVB_TXD4 — — — —
IP12[21:20] ETH_TXD0 AVB_TXD5 — — — —
IP12[23:22] ETH_MDC AVB_TXD6 — — — —
IP12[26:24] — AVB_TXD7 SCIFB2_TXD_D — MSIOF0_SYNC_C —
IP12[29:27] — AVB_TX_EN SCIFB2_RXD_D — MSIOF0_SCK_C —
Legend:
—
Setting prohibited