QUANTA QSSC-S99K 2U, Руководство пользователя

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Memory RAS
1. Independent Channel Mode
Channels can be populated in any order in Independent Channel Mode. All three channels may be populated in any order
and have no matching requirements. All channels must run at the same interface frequency, but individual channels may
run at different DIMM timings (RAS latency, CAS latency, etc.).
2. Mirrored Channel Mode
In Mirrored Channel Mode, the memory contents are mirrored between Channel 0 and Channel 1. As a result of the
mirroring, the total physical memory available to the system is half of what is populated. Mirrored Channel Mode
requires that Channel 0 and Channel 1 must be populated identically. DIMM slot populations within a channel do not
have to be identical but the same DIMM slot location across Channel 0 and Channel 1 must be populated the same.
Channel 2 is unused in Mirrored Channel Mode.
3. Mirrored Channel Mode
In Lockstep Channel Mode, each memory access is a 128-bit data access that spans
Channel 0 and Channel 1. This is done to support SDDC for DRAM devices with 8-bit wide data ports. The same address
is used on both channels such that an address error on any channel is detectable by bad ECC. Lockstep Channel mode is
the only RAS mode that supports x8 SDDC. Lockstep Channel Mode requires that Channel 0 and Channel 1 must be
populated identically. That is, each DIMM in one channel must have a corresponding DIMM of identical organization
such as number of ranks, banks, rows, and/or columns. DIMMs may be of different speed grades, but the Integrated
Memory Controller will be configured to operate all DIMMs according to the slowest parameters present. DIMM slot
populations within a channel do not have to be identical but the same DIMM slot location across Channel 0 and Channel
1 must be populated the same. Channel 2 is unused in Lockstep Channel Mode.
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Chapter 3 — BIOS