PLX Technology PEX 8311RDK, Справочник по аппаратуре

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PEX 8311RDK Hardware Reference Manual, Version 0.90
28 © 2005 PLX Technology, Inc. All rights reserved.
Table 4-8. Programming the Xilinx Uncommitted FPGA through the GPIO
PEX 8311
signal
Link Resistor
(value)
FPGA signal [pin]
Pull-up resistor
or jumper
Pull-down
resistor or
jumper
GPIO3 R180 (56 Ω ) PROG_B [1] JP5 NC -
USERi R347 (0) DONE [72]
R348 (0) +
R358 (330 Ω )
1
-
GPIO2 R292 (0) INIT_B [40]
JP4 NC + R116
(4K7)
-
VCC R309 (0) M0 [62] R368 (10K) -
VCC R297 (0) M1 [60] R350 (10K) -
VCC R284 (0) M2 [57]
2
R367 (10K) -
GPIO1 R315 (0) DIN [63] JP3 NC -
GPIO0 R345 (56 Ω ) CCLK [71] JP2 NC -
Notes:
1) R348 and R353 are only required if BitGen option DriveDONE = No – see the appropriate Xilinx
data sheet for more details. Ideally pin 3 or pin 6 of RN10 should be lifted if R348 and R353 are
used.
2) If LA19 is connected to this pin through R283 then R284 and R367 are not required as this pin is
pulled high using RN11.
In addition to the above resistors the appropriate power supply and ground resistors must also be
populated.
4.4.2.3.3 Programming the uncommitted FPGA from the configuration PROM
Xilinx FPGA’s can be configured using Platform Flash In-System Programmable Configuration PROMs.
FP1 is designed to accept the VO20/VOG20 packaged versions of the XCFxxS platform flash PROMs.
Table 4-9 details the resistor configurations required to interface a platform flash assembled on FP1 to a
Xilinx Spartan-3E array assembled on FP2.
It also details the resistor options for connecting the platform flash JTAG interface to JP7 to allow the
platform flash to be programmed using the JTAG interface. JP7 is the 14 pin Target Interface connector
(e.g. Molex part no. 87831-1420) and can be used with appropriate programmers from Xilinx to configure
the device using the JTAG interface.
The programming method detailed in Table 4-9 is master serial mode. Other programming modes may
also be selected using the appropriate resistor options. The JTAG TDO output from the platform flash is
routed to the TDI input of the Xilinx FPGA. If the JTAG interface is not required the resistors marked with
a † in Table 4-9 may be removed.
Depending on the device and power supplies used it may be necessary to add a resistor from the 2.5V
rail to ground to manage reverse current. Typically this resistor would be 118
Ω or 110 Ω and would only be
required if the 2.5V supply for the FPGA was sourced from the USRVCC – see the Xilinx application notes for further
details regarding reverse currents.