PLX Technology PEX 8311RDK, Справочник по аппаратуре

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PEX 8311RDK Hardware Reference Manual, Version 0.90
© 2005 PLX Technology, Inc. All rights reserved.
23
FPGA
Pin No.
Xilinx Pin
Name
Altera Pin
Name
Local Signal
Bus
No.
Xilinx link
resistor
Xilinx
Voltage R
Xilinx
Capacitor
Altera link
resistor
Altera
Voltage R
Altera
Capacitor
101 IP GND LA22_X C29 424 426 475
102 2.5V 3.3V C30 429 463 134 428 481 140
103 I/O I/O DP0 C31 432 432
104 I/O I/O DP1 C32 435 435
105 I/O I/O DP2 C33 438 438
106 I/O I/O DP3 C34 441 441
107 IP I/O LA30/DEN# C35 444 444
108 TMS I/O LA3_A C36 172 449
109 TDO I/O LA15_A D1 171 493
110 TCK I/O LA21_A D2 170 497
111 IP I/O LA23 D3 502 502
112 I/O I/O DREQ1# D4 507 507
113 I/O I/O LBR1 D5 510 510
114 IP I/O LA24 D6 513 513
115 1.2V 3.3V D7 520 509 142 520 501 142
116 I/O GND LA13_X D8 523 524 598
117 I/O 1.5V LA14_X D9 530 532 536 143
118 GND GND D10 538 547 537 620
119 IP I/O LA25 D11 542 542
120 IP I/O LA26 D12 548 548
121 3.3V I/O LA22_A D13 562 144 554
122 I/O I/O LD13 D14 558 558
123 I/O I/O LINTi# D15 563 563
124 I/O I/O LRESET# D16 568 568
125 I/O I/O LBE0# D17 573 573
126 I/O I/O LBE1# D18 578 578
127 GND I/O D19 594 User IO
128 GCLK8 I/O LCLK_T D20 496 User IO
129 IP I/O D21 User IP User IO
130 I/O I/O LW/R# D22 505 505
131 I/O I/O LD14 D23 508 508
132 I/O I/O READY# D24 511 511
133 GND I/O LA28_A D25 518 615 516
134 I/O I/O WAIT# D26 521 521
135 I/O 1.5V LA3_X D27 526 528 605 150
136 IP GND LA28_X D28 533 534 621
137 2.5V 3.3V D29 540 585 146 540 580 146
138 3.3V GND D30 545 603 153 545 618
139 I/O I/O LD20 D31 551 551
140 I/O I/O LD21 D32 555 555
141 IP I/O LA27 D33 559 559
142 I/O I/O LBE2# D34 564 564
143 I/O I/O LBE3# D35 569 569
144 TDI I/O PMEIN#_A D36 173 574
Notes:
1) The resistors used for the Xilinx programming pins will depend on the programming method used.
Refer to Table 4-6, Table 4-8 and Table 4-9 for further details.
2) The resistors used for the Altera programming pins will depend on the programming method used.
Refer to Table 4-5, Table 4-7 for further details.
With the exception of the resistors noted in Table 4-5, Table 4-6, Table 4-7, Table 4-8 and Table 4-9 the
resistor value will normally be 0 ohms.
Depending on the I/O of the FPGA some additional signal noise may be seen. If this is the case then the
value of the resistors used to link to the local bus signals may be increased to form a series termination
resistor. The value required will depend on the loading but will typically be in the range of 30 to 100 ohms.