PLX Technology PEX 8311RDK, Справочник по аппаратуре

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PEX 8311RDK Hardware Reference Manual, Version 0.90
4 © 2005 PLX Technology, Inc. All rights reserved.
3. PEX 8311RDK Hardware Architecture
PEX8311
PCI Express x1
Link
Serial
EEPROMs
Local Bus
Clock Circuit
66MHz
LOCAL BUS
Up to 32-bit 66MHz
Address Bus
Data bus
Control Bus
POM Connector Test Headers
Synchronous
SRAM
32Kx32
SRAM
Controller
Data Bus
Ready#
Memory
Address
Bus
Controls
PEX 8311 RDK Hardware Block Diagram
7
32
8
SRAM Controller
Arbiter
Chip Select
Generator
Controls
8
Address
Xilinx CPLD
Bterm#
PCI Express
100MHz clock
PCI Express
100MHz Clock
Circuit
(not populated)
Midbus
Connector
(not
populated)
x
1
P
C
I
E
x
p
r
e
s
s
C
a
r
d
E
d
g
e
PCI Express
Pushbutton
Reset Circuit
Prototyping
Area &
Footprints
LED's for
GPIO's and
power
supplies
Internal Clock
Circuit
66MHz (not
populated)
Local
Clock
Figure 3-1. PEX 8311RDK Hardware Architecture
3.1 PEX 8311 PCI Express Bridge Device
The PEX 8311 (U1) is a high-performance PCI Express to local bus device that enables designers to
migrate legacy designs to the new, advanced serial PCI Express. This 2-port device is equipped with a
single-lane PCI Express port and a parallel local bus segment supporting multiplexed (J mode) and non-
multiplexed (C Mode) operating modes. The PEX 8311 is capable of operating as an Endpoint or a Root
Complex. The PEX 8311 bridge device is housed in a 21 x 21 mm, 337-ball PBGA package. Ball spacing
is 1.0 mm. No additional cooling is required.
The PEX 8311 supports Direct Slave and Direct Master data transfers; in addition there are two DMA
channels, and an Intelligent Messaging Unit. For more detailed information about the PEX 8311 please
see the PEX 8311 data book.
3.2 Serial EEPROM
The PEX 8311 bridge device has two EEPROM’s associated with it. These EEPROM’s can be used to
load configuration data on power-up.