PLX Technology PEX 8311RDK, Справочник по аппаратуре

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PEX 8311RDK Hardware Reference Manual, Version 0.90
© 2005 PLX Technology, Inc. All rights reserved.
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4.1.3 Indicators
By default GPIO[3:1] are configured as inputs and pulled high.
GPIO0 (and LED0) shows the link status.
By changing GPIOCTL[13:12] in the SPI EEPROM (U2) the GPIO[3:0] lines and LED[3:0] can be
reconfigured to reflect the lower four bits of the LTSSM state machine. See the PEX8311 data book for
additional details.
The other LED’s on the PEX 8311 indicate operation of the power supplies as detailed in Table 3-4. PEX
8311RDK LED Indicators
4.1.4 Controls
Table 4-1. PEX 8311RDK Default Jumper Settings
Jumper Factory Setting Description
JP1 OPEN Pull down BAR0ENB# when closed
JP2 OPEN GPIO0 drives LED1
JP3 1-2 Pull GPIO1 high
JP4 1-2 Pull GPIO2 high
JP5 1-2 Pull GPIO3 high
J7 CLOSED +3.3V supply to PEX 8311
J8 CLOSED +1.5V supply to PEX 8311
J9 CLOSED +2.5V supply to PEX 8311
4.2 PEX 8311RDK Layout Information
4.2.1 Trace Routing Design Rules
The characteristic trace impedances are within the PCI Express specification (100 Ohm ±5%) for the
differential, and within the PCI specification (55 Ohm ±10%) for the single-ended.
4.2.2 Power Decoupling
Power decoupling is provided by two means – plane capacitance (provided by the PCB stackup) and
discrete decoupling capacitors. Plane capacitance filters noise above approximately 100 MHz. The
footprints for the discrete decoupling capacitors are designed such that the inductance between the pad
and plane is reduced by careful via placement. (Refer to Figure 4-2. PEX 8311RDK Decoupling Capacitor
Footprints)