PLX Technology PEX 8311RDK, Справочник по аппаратуре

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PEX 8311RDK Hardware Reference Manual, Version 0.90
30 © 2005 PLX Technology, Inc. All rights reserved.
The uncommitted regulator can be fed from either the PCIE3.3VCC rail (populate R175) or from the 5V
supply provided by the ATX connector J4 (populate R174).
The uncommitted USRVCC could also be used to provide an additional 1.5VCC as there is relatively little
spare current available from U3.
It should be noted that not all power rails are available for all the Vx bus resistor options associated with
FP2 and it may be necessary to wire directly from the regulator to the appropriate PFx hole under some
circumstances.
4.4.2.5 Uncommitted FPGA Pull-ups/downs
Many of the pins associated with the uncommitted FPGA footprint can be pulled high or low. These pulls
are set up using the appropriate resistor to link to a Vx bus and then selecting the voltage the pin should
be pulled to using a second resistor.
FPGA pins which are connected to LA or control pins of the PEX 8311 will not normally require additional
pulls as these are already pulled to the correct value – see sheet 3 of the schematics.
4.4.2.6 Increasing the number of unused uncommitted FPGA I/O
The vast majority of the I/O of the FPGA’s are used in connecting to the PEX 8311. The settings detailed
in section 4.4.2.2 show the FPGA connected to the PEX 8311 in C mode using a 32 bit data bus. In
addition every feature of the PEX 8311 is connected to the FPGA.
For some applications more FPGA I/O will be required for user circuitry attached to the FPGA. There are
several ways in which additional I/O can be released:
1) C mode of J mode
When operating in C mode both the address and data buses have to be routed to the FPGA. If
the board is re-configured to operate in J mode (see section 5) those signals which were
previously allocated to the LA bus are no longer required and can be used as additional I/O.
2) Data bus width
The data bus is currently configured to be a 32 bit bus. The LBRDx registers can be reconfigured
to allow operation in 8 or 16 bit mode, thereby releasing the I/O which are connected to the
unused data lines.
It may be useful to only change LDRD1 to a different bus width. This will allow 32 bit accesses to
the SBSRAM using local address space 0.
It should be noted that if the FPGA is to access any of the PEX 8311 registers that access must
be a 32 bit wide access so reducing the bus width is really only a solution for slave designs.
3) Bus Mastering or Slave only designs
If the FPGA is only going to be used as a slave device then it may not be necessary to link all of
the local bus control signals to the FPGA.
4) Address bus subset
CS3# is routed to the FPGA and can be used as a chip select for the device. If only a small
number of addresses are going to be decoded by the FPGA the upper portion of the LA bus can
be left unconnected releasing FPGA I/O.