PEX 8311RDK Hardware Reference Manual, Version 0.90
2
© 2005 PLX Technology, Inc. All rights reserved.
1.1
PEX 8311 Features
Compliant
to
PCI Express Base Specification, Revision 1.0a
Local bus and register compatibility with PCI 9056 and PCI 9656 allows systems to migrate to
PCI Express and leverage software compatibility
Integrated single PCI Express port and interface with x1 link, dual-simplex 2.5 Gbps SerDes
Configurable local bus supporting 8, 16 and 32 bit local bus architectures
Multiplexed and non-multiplexed local bus operation
Powerful high performance DMA engine supporting block, scatter gather, ring management and
demand mode
Supports Endpoint and Root
Complex Modes
Small package, enabling compact design
Low power consumption
3.3V I/O and 5V tolerant local bus
Serial EEPROMs used for optional boot configuration with Serial Peripheral Interface (SPI) and
Microwire Interface
8-KB general-purpose shared RAM
1.2
PEX 8311RDK Features
PLX PCI Express-to-PCI bridge device in a 21 x 21 mm, 337-ball PBGA package
Single x1 PCI Express Edge connector for insertion into standard PCI Express slot of x1 or
greater link width
Supports 32-bit C (default) or J mode Processor/Local Bus operation with speeds up to 66MHz
128KB synchronous burst SRAM with the CPLD memory controller demonstrates the PEX 8311
continuous burst feature
Jumpers for PEX 8311 hardware configuration
Socketable SPI and Microwire serial EEPROMs (3.3V devices supported)
Onboard probing points and logic analyzer connections
LEDs for link status visual inspection and power supply operation
Auxiliary ATX hard disk connector for additional power requirement support
Prototyping area with five (5) surface mount footprints, one (1) voltage regulator footprint, and
one (1) 20x10, 0.1” through-hole grid
Pushbutton reset module
Socketed oscillator for Processor/Local Bus clock and local logic
PLX J-Bus Option Module (POM) connector for expansion
Option for on board PCI Express reference clock generation
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