PLX Technology PEX 8311RDK, Справочник по аппаратуре

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PEX 8311RDK Hardware Reference Manual, Version 0.90
© 2005 PLX Technology, Inc. All rights reserved.
7
Table 3-2. Extra Long Serial EEPROM Load Registers
Serial
EEPROM
Offset
Serial
EEPROM
Hex Value
Description Register Bits Affected
44h 8311 Subsystem ID PCISID[15:0]
46h 10B5 Subsystem Vendor ID PCISVID[15:0]
48h FFFE MSW of Range for PCI-to-Local Address Space 1 LAS1RR[31:16]
4Ah 0000 LSW of Range for PCI-to-Local Address Space 1 LAS1RR[15:0]
4Ch 0000
MSW of Local Base Address (Re-map) for
PCI-to-Local Address Space 1
LAS1BA[31:16]
4Eh 0001
LSW of Local Base Address (Re-map) for
PCI-to-Local Address Space 1
LAS1BA[15:0]
50h 0000
MSW of Bus Region Descriptors for
PCI-to-Local Address Space 1
LBRD1[31:16]
52h 01C3
LSW of Bus Region Descriptors for
PCI-to-Local Address Space 1
LBRD1[15:0]
54h 0000 Hot Swap Control/Status Register Reserved
56h 4C06
Hot Swap Control/Status Register /
Hot Swap Next Capability Pointer
HS_NEXT[7:0] / HS_CNTL[7:0]
58h 0000 Reserved Reserved
5Ah 0000 PCI Arbiter Control PCIARB[15:4] / PCIARB[3:0]
5Ch 7A02 Power Management Capabilities PMC[15:9,2:0]
5Eh 4801
Power Management Next Capability Pointer /
Power Management Capability ID
(the LSB is reserved)
PMNEXT[7:0] / PMCAPID[7:0]
60h 0000
Power Management Data /
PMCSR Bridge Support Extensions
(the LSB is reserved)
PMDATA[7:0]/ PMCSR_BSE[7:0]
62h 0000
Power Management Control/Status
(Bits 15, 7:2, and 1:0 are reserved)
PMCSR[15:0]
3.3 Local and PCI Express Hardware Elements
As shown in Figure 3-1, the RDK hardware contains:
•
PEX 8311 PCI Express I/O Accelerator
•
Four PEX 8311 Local Bus components (Local clock distribution, CPLD, SBSRAM, Test Headers,
and POM connector)
•
LED’s for GPIO and power supply status
•
Small prototyping area – including an uncommitted FPGA footprint
•
PCI Express Reset Circuitry (see section 3.4.2.1 Reset Circuitry)
• A hardware development module for PCI Express clock generation (see section 3.4.1 RefClk)
•
A hardware development module for the PEX 8311 internal reference clock (see section 3.3.4
Internal Clock)
The RDK’s Local Bus is pre-configured for non-multiplexed address and data bus operation (C mode), but
it is user-configurable to allow multiplexed address and data operation (J Mode). (See Section 5 RDK
Mode Configuration for details on re-configuring the RDK hardware for J Mode operation.) Once the
board is correctly installed into a PC computer system, a host, such as the motherboard’s processor, can
perform single cycle memory read/write cycles, multiple memory read/write cycles, and burst memory
read/write cycles from/to the on-board SBSRAM in Direct Slave mode. The host can also program the
PEX 8311 to perform DMA data transfers between the PCI Express bus and the SBSRAM.