PLX Technology PEX 8311RDK, Справочник по аппаратуре

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Title
Size Document Number Rev
Date: Sheet of
000
PEX8311RDK-Lite
PLX TECHNOLOGY, INC.
870 Maude Ave, Sunnyvale, CA 94085
Custom
1 15 Wednesday, December 14, 2005
www.plxtech.com
Title
Size Document Number Rev
Date: Sheet of
000
PEX8311RDK-Lite
PLX TECHNOLOGY, INC.
870 Maude Ave, Sunnyvale, CA 94085
Custom
1 15 Wednesday, December 14, 2005
www.plxtech.com
Title
Size Document Number Rev
Date: Sheet of
000
PEX8311RDK-Lite
PLX TECHNOLOGY, INC.
870 Maude Ave, Sunnyvale, CA 94085
Custom
1 15 Wednesday, December 14, 2005
www.plxtech.com
On-Board Prototyping Area
- 144-pin PLCC Footprint for Altera or Xilinx FPGA
- SMD device footprints
- Power Regulator circuit (un-populated)
- Thru-hole grid, 20x10, 0.1" spacing
Daughter Board Conn.
use AMP p/n 6-104652-0
Custom Daughter Card
Mounting Area
Test Headers
JTAG
Catalyst Mid-Bus LAI Footprint
LCLK
Osc.
PCI Express
Clock Gen.
(not populated)
LCLK
Dist.
ATX HDD
Pwr. Conn
Molex
53109-0410
Power Regulators
JTAG
PEX 8311
+12 V
+3.3 V +12 V
+5.0 V
© 2005 PLX Technology, Inc. All rights reserved.
PLX Technology, Inc. retains the right to make changes to this product at any time, without notice.
Products may have minor variations to this publication, known as errata.
PLX assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of PLX products.
PLX Technology and the PLX logo are registered trademarks of PLX Technology, Inc.
Other brands and names are the property of their respective owners.
+3.3 V
+2.5 V
+1.8 V
Table Of Contents Block Diagram Revision History
Date Summary of Changes 01: Cover Page
02: PEX8311 PCI Express Bus
03: PLX8311 Local Bus
04: CPLD and SBSRAM
05: Test Headers
PCIE Clock Gen
06: PLX Option Module Connector
07: Catalyst Midbus and
08: FPGA Footprint
09: FPGA Side A Option Resistors
10: FPGA Side B Option Resistors
11: FPGA Side C Option Resistors
12: FPGA Side D Option Resistors
15: NC Balls
13: Pads
14: Prototype Footprint
PCI Express X1
Card-Edge Connector
AT25640A
SPI EEPROM
(PCIE Config.)
Xilinx XC9572XL CPLD
- SBSRAM controller
- Chip Selects
- Local Bus Arbiter
32bit, 66.666Mhz PLX Local Bus
Samsung K7B403625B
Synchronous Burst SRAM
(Flow-Through Outputs)
512 Kbytes
93CS56/66
u-Wire EEPROM
(Local Bus Config.)
Daughter Board Header
AMP p/n 6-104655-1
On-board
Reset Gen.
12-08--05 Release 1.0
91-0058-000-A
This schematic includes minor board errata's which are not implemented in the PCB layout. See PEX8311RDK Errata Rev. 1.0, Dec. 2005 for details.