Omron SYSMAC CQM1H Series, Руководство по программированию

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Appendix A
Programming Instructions
A PC instruction is input either by pressing the corresponding Programming Console key(s) (e.g., LD, AND,
OR, NOT) or by using function codes. To input an instruction with its function code, press FUN, the function
code, and then WRITE. Refer to the pages listed programming and instruction details.
Code Mnemonic Name Function Page
— AND AND Logically ANDs status of designated bit with execution condi-
tion. 222
— AND LD AND LOAD Logically ANDs results of preceding blocks. 223
— AND NOT AND NOT Logically ANDs inverse of designated bit with execution condi-
tion. 222
— CNT COUNTER A decrementing counter. 235
— LD LOAD Used to start instruction line with the status of the designated
bit or to define a logic block for use with AND LD and OR LD. 222
— LD NOT LOAD NOT Used to start instruction line with inverse of designated bit. 222
— OR OR Logically ORs status of designated bit with execution condi-
tion. 222
— OR LD OR LOAD Logically ORs results of preceding blocks. 223
— OR NOT OR NOT Logically ORs inverse of designated bit with execution condi-
tion. 222
— OUT OUTPUT Turns ON operand bit for ON execution condition; turns OFF
operand bit for OFF execution condition. 224
— OUT NOT OUTPUT NOT Turns operand bit OFF for ON execution condition; turns oper-
and bit ON for OFF execution condition (i.e., inverts opera-
tion). 224
— RSET RESET Turns the operand bit OFF when the execution condition is
ON, and does not affect the status of the operand bit when the
execution condition is OFF. 224
— SET SET Turns the operand bit ON when the execution condition is ON,
and does not affect the status of the operand bit when the exe-
cution condition is OFF. 224
— TIM TIMER ON-delay (decrementing) timer operation. 234
00 NOP NO OPERATION Nothing is executed and program moves to next instruction. 227
01 END END Required at the end of the program. 227
02 IL INTERLOCK If interlock condition is OFF, all outputs are turned OFF and all
timer PVs reset between this IL(02) and the next ILC(03).
Other instructions are treated as NOP; counter PVs are main-
tained. 227
03 ILC INTERLOCK CLEAR 227
04 JMP JUMP If jump condition is OFF, all instructions between JMP(04) and
the corresponding JME(05) are ignored. 229
05 JME JUMP END 229
06 (@)FAL FAILURE ALARM AND
RESET
Generates a non-fatal error and outputs the designated FAL
number to the Programming Console. 230
07 FALS SEVERE FAILURE
ALARM Generates a fatal error and outputs the designated FALS num-
ber to the Programming Console. 230
08 STEP STEP DEFINE When used with a control bit, defines the start of a new step
and resets the previous step. When used without N, defines
the end of step execution. 231
09 SNXT STEP START Used with a control bit to indicate the end of the step, reset the
step, and start the next step. 231
10 SFT SHIFT REGISTER Creates a bit shift register. 261
11 KEEP KEEP Defines a bit as a latch controlled by set and reset inputs. 225