106
AR Area
Section 6-4
AR 19
00
Pulse output 1 com-
mands
PV Reset
OFF: Pulse output 1 PV
not reset
ON: Pulse output 1 PV
reset
User
Enabled
01
Range Compari-
son Result Clear
OFF: The instruction
execution result (AR 20)
or the output bit pattern
(AR 21) that is output
when the CTBL instruc-
tion is executed for a
range comparison on the
pulse output PV is not
cleared.
ON: The instruction exe-
cution result (AR 20) or
the output bit pattern
(AR 21) that is output
when the CTBL instruc-
tion is executed for a
range comparison on the
pulse output PV is
cleared.
02 to 06
(Reserved by system.)
07
Common for both pulse
output 1/2
Speed-changing
cycle
OFF: Set 2 ms to the
speed-changing cycle
for acceleration and
deceleration of ACC and
PLS2 instructions
ON: Set 1 ms to the
speed-changing cycle
for acceleration and
deceleration of ACC and
PLS2 instructions
(HCP22-V1 only)
08
Pulse output 2 com-
mands
PV Reset
Same as for pulse output
1 commands.
09
Range Compari-
son Result Clear
10 to 13
(Reserved by system.)
14
Common for both pulse
output 1/2
PLS2 instruction
Absolute posi-
tion mode
change (-V1
only)
OFF: Give the priority to
Direction designation
When the direction of
the pulse output is same
as the direction of the
absolute position, the
pluses are output.
ON: Give the priority to
Absolute position
The pulse are output by
the direction of the abso-
lute position.
15
PLS2 instruction
mode change
(-V1 only)
OFF: Normal mode (out-
puts pulse to external
device)
ON: Virtual pulse output
mode (executes virtual
pulse output, without
actual pulse output to
external device)
Address
Bits
Function
Details
Controlled
by
Forced
set/reset
Содержание CS1W-HCA12-V1
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Страница 20: ...xx Conformance to EC Directives 7...
Страница 38: ...18 Models and System Configurations Section 1 2...
Страница 78: ...58 Fail safe Circuits Section 3 5...
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