136
Pulse Outputs
Section 7-6
7-6-5
Speed-Changing Cycle Selection of ACC/PLS2 Instructions and
Widening of Acceleration/Deceleration Setting Ranges
With the -V1 unit with lot No. 0209__ or later, the speed-changing cycle for
acceleration and deceleration of ACC and PLS2 instructions can be selected
from 1 ms or 2 ms. The speed-changing cycle of ACC and PLS2 instructions,
and of port 1 and 2 have to be the same. Additionally, the setting ranges for
acceleration and deceleration have been widened from 1 Hz to 2 kHz to 1 Hz
to 9.999 kHz.
Switching the Speed-
changing Cycle of ACC/
PLS2 Instructions
The speed-changing cycle for acceleration and deceleration of ACC and
PLS2 instructions can be switched by the setting (ON/OFF) of bit 07 of AR 19
prior to the execution of the instructions.
2 ms Cycle
Execute ACC or PLS2 instruction with bit 07 of AR 19 OFF.
1 ms Cycle
Execute ACC or PLS2 instruction with bit 07 of AR 19 ON.
7-6-6
Pulse Output Direction and Absolute Position Designation
Priority Modes
With -V1 lot No. 0209 or later Units, the direction that pulses are output by the
PLS2 instruction depends on the priority mode that is selected. The direction
may be determined automatically from the absolute position using absolute
position designation as the priority mode, or it may be specified by a user-
defined operand using the pulse output direction as the priority mode.
With Units prior to -V1 lot No. 0209, no pulses were output unless the output
direction designated by the PLS2 instruction was the same as the output
Execution
condition
@ACC
001
000
DM 0000
DM 0000
DM 0001
DM 0002
2000
0000
0005
Accel/decel: 2 kHz
Target speed: 50 kHz
AR 19.07
2000
0000
0005
Accel/decel: 2 kHz
Target speed: 50 kHz
DM 0000
DM 0001
DM 0002
@ACC
001
000
DM 0000
Always ON
Execution condition
Содержание CS1W-HCA12-V1
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