P4080 Development System User’s Guide, Rev. 0
Freescale Semiconductor
51
Programming Model
7.1.9
SRAM Address Register (PX_ADDR)
The SRAM address register (PX_ADDR) is a general-purpose register that is used to index an internal
256-byte SRAM array. Though reset upon initial power activation or by chassis reset sources, PX_ADDR
preserves its value between COP- or watchdog-initiated resets.
NOTE
Writing PX_ADDR and reading/write PX_DATA is non-atomic. Care
should be exercised when sharing SRAM between processors and/or the
ngPIXIS GMSA core.
7.1.10
Data Register (PX_DATA)
The data register (PX_DATA) is a general-purpose register that is used to read or write to an internal
256-byte SRAM array. Though reset upon initial power activation or by chassis reset sources, PX_DATA
preserves its value between COP- or watchdog-initiated resets.
5–6
—
Reserved
7
SD8X
0 P4080 SPI_CS(0:3)_B pins are used as SDHC data bits 4:7 for SDHC-8bit mode. SPI CS_B pins are
pulled high.
1 P4080 SPI_CS(0:3)_B pins are used with the SPI controller. SDHC data bits 4:7 are pulled high and
only SDHC 4-bit mode is used.
Offset 0x0A
Access: Read/Write
0
7
R
ADDR
W
Reset
All zeros
Figure 34. SRAM Address Register (PX_ADDR)
Table 31. PX_ADDR Field Descriptions
Bits
Name
Description
0–7
ADDR
Address of SRAM array to which PX_DATA reads/writes.
Offset 0x0D
Access: Read/Write
0
7
R
DATA
W
Reset
All zeros
Figure 35. Data Register (PX_DATA)
Table 30. PX_BRDCFG0 Field Descriptions (continued)
Bits
Name
Description