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P4080 Development System User’s Guide, Rev. 0
36 Freescale Semiconductor
Architecture
In addition, the SNAPSHOT command allows collection of data, including paired voltage and current
measurements. See the ZL2006 data sheet and the PMBus association specifications for further details.
5.3.2 GVDD/VTT DDR Power
The P4080DS uses the Zilker Labs ZL2006 switching power controller as a single-phase controller for up
to 22 A of power at a nominal 1.5-V output. As with the Core and Platform power regulators, the PMBus
may be used; however, there are no switchable values. This device supplies both GVDD, while an LDO,
it supplies half of this voltage as VTT (termination power), and MVREF (switching reference voltage) for
the DDR DIMM and the P4080 DDR interface.
5.3.3 XVDD/SVDD SerDes Power
XVDD is a filtered copy of the DDR power GVDD. There is a backup LDO as an alternative source of
XVDD. Filtering is the primary choice, while the LDO is for experimentation. SVDD is a filtered copy of
Platfom power VDD_PL.
5.4 Clocks
This table summarizes the clock requirements of the P4080DS. Note that the DDR clocks are not included,
because they are provided by the P4080.
Table 15. P4080DS Clock Requirements
Clock Destination
Clock
Frequency
Specs Type Notes
SYSCLK P4080 SYSCLK 33–200 MHz t
R
<= 1ns
t
F
<= 1ns
<= 60% duty
<= 150 ps jitter
LVTTL 133.33 nominal
closed loop jitter bandwidth
should be <500 kHz at
20 dB.
BCLK P4080 RTCCLK 14.318 MHz none LVTTL —
P4080 SD1_REFCLK(p,n) 100.00 MHz
or
125.00 MHz
jitter: 80–100 ps
skew: 330 ps LVDS 100.00 MHz
100 ps jitter
SD1 REFCLK SLOT1 REFCLK(p,n) — — — —
SLOT2 REFCLK(p,n) — — — —
SLOT3 REFCLK(p,n) — — — —
SD2 REFCLK P4080 SD2_REFCLK(p,n) 156.25 MHz
or
125.00 MHz
— — —
SLOT4 REFCLK(p,n) — — — —
SD3 REFCLK P4080 SD3_REFCLK(p,n) 156.25 MHz
or
125.00 MHz
— — —
SLOT5 REFCLK(p,n) — — — —