NXP Semiconductors P4080, Руководство пользователя, Страница: 39 / 60

P4080 Development System User’s Guide, Rev. 0
Freescale Semiconductor 39
Architecture
5.4.1 SYSCLK
Much of the timing within the P4080 is derived from the SYSCLK input. On the P4080DS, this pin is
controlled by an IDT ICS307-02 frequency synthesizer. This device is serially configured by 20 found bits
of data by the ngPIXIS as part of the reset/power-up sequence. These 24 bits can be controlled to set the
SYSCLK speed to fine increments using the dynamic (re)configuration facilities of remote access
ngPIXIS. To make configuration easy, ngPIXIS pre-loads the 24-bit configuration pattern using one of
eight popular values by sampling three switches located on the motherboard. This table summarizes the
switch-selectable clock generation possibilities.
Table 16 is based upon a 33.333-MHz reference clock input. The “Control Word” field is the data sent to
the ICS307 upon startup, or when commanded to by the VELA controller. This value can be calculated
from the ICS307 data sheet examples, or using the convenient online calculator IDT provides. In the cases
above, whenever different values are calculated for frequency accuracy vs. lowest-jitter, the lowest-jitter
parameter was chosen.
5.5 System Reset
The P4080DS ngPIXIS contains a reset sequencer used to properly manage the orderly bring-up of the
system (this is not the same as the power sequencer, which is similar, but not specifically related to reset).
Once the system has transitioned to having fully stable power supplies, the reset sequencer waits for all
reset conditions to clear, configures and releases the processor from reset, then idles waiting for further
reset conditions to occur. This table summarizes reset conditions and actions.
Table 16. SYSCLK Frequency Options
cfg_sysclk Selected SYSCLK Actual SYSCLK Error ICS307 Control Word Notes
0 0 0 66.666 MHz 66.6660 MHz 0 ppm 0x270501 —
0 0 1 75.000 MHz 74.999 MHz 10 ppm 0x230984 —
0 1 0 83.333 MHz 83.3325 MHz 6 ppm 0x230381 —
0 1 1 90.000 MHz 89.999 MHz 10 ppm 0x230983 —
1 0 0 100.000 MHz 99.9990 MHz 10 ppm 0x230501 —
1 0 1 111.000 MHz 111.110 MHz 9 ppm 0x260381 —
1 1 0 125.000 MHz 124.998 MHz 10 ppm 0x210382 —
1 1 1 133.333 MHz 133.332 MHz 7.5 ppm 0x210201 —
Table 17. Reset Terms
Term Type Description Notes
HOT_RST_B External HOT power stable Restarts all ngPIXIS internal state machines and registers
PWRGD External ATX power stable Causesfull system reset unless the system is in S3 (power
down) state.
COP_HRST_B External COP tool reset request Triggers reset, but must never cause CPU_TRST_B to be
asserted