NXP Semiconductors P4080, Руководство пользователя, Страница: 27 / 60

P4080 Development System User’s Guide, Rev. 0
Freescale Semiconductor 27
Architecture
5.1.16 Debug and Power Management
This table summarizes the debug and power management signals.
5.1.17 Clock
This table summarizes the clocks for the P4080. Further details on the clock architecture are covered in
Section 5.4, “Clocks . ”
NOTE
The SerDes and Ethernet clocks are included in their respective sections.
5.1.18 Temperature
The P4080 has two pins connected to a thermal body diode on the die, allowing direct temperature
measurement. These pins are connected to the ADT7461 thermal monitor, which allows direct reading of
the temperature of the die and is accurate to ±1 °C. This figure shows the thermal management scheme for
the P4080DS.
EMI2 10 No DeviceI
EMI2 11 Slot 5 XAUI
Table 13. Debug and Power Management Connections
Signal Names Connections
EVT[2,3,7,8] P6880 Debug header
MSRCID[0:2] P6880 Debug header
MDVAL P6880 Debug header
CLK_OUT Test point w/adjacent ground.
ASLEEP ngPIXIS
LED
Table 14. P4080 Clock Connections
Pin Count Signal Names Connections
1 SYSCLK ICS307 System clock synthesizer
1 RTC Arbitrary timebase frequency
11 Total pins in this group
Table 12. PHY Management Bus Map for EMI2 (continued)
Bus GPIO[2:3] Device