P4080 Development System User’s Guide, Rev. 0
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Freescale Semiconductor
Architecture
Note that this is the power for the P4080 only as implemented on the P4080DS; it does not include external
devices, memory, and so on. Because these are estimates, and because alpha silicon tends to be “hot,” the
VDD rail must have an excess capacity of approximately 20%.
Note also that the P4080 supports more than these voltage levels, but they are the voltage levels supported
by the P4080DS.
Because of the high-current transients present on the VDD power pins, careful attention should be paid to
properly bypass these power pins and to provide a good connection between the BGA pads and the power
and ground planes. In particular, the SMD capacitors should have pads directly attached to the via ring (or
within it, if the PCB costs are not prohibitive).
5.2
System Control Logic
The P4080DS contains an FPGA, the ngPIXIS, which implements the following functions:
•
Reset sequencing/timing combined with COP/JTAG connections.
•
Map/re-map P4080 local bus chip selects to Flash, compact Flash, and so on.
•
Transfer switch settings to processor/board configuration signals.
•
Load configuration data from RAM (registers) or EEPROM to override configuration for self-test.
•
Miscellaneous system logic
— COP reset merging
— DMA trigger/monitor registers
— I
2
C timeout reset
The FPGA is powered by standby power supplies and an independent clock. This allows the FPGA to
control all aspects of board bringup, including power, clocking, and reset.