NXP Semiconductors MC9S08LG16, Справочное руководство

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Chapter 19 Debug Module (DBG) (64K)
MC9S08LG32 MCU Series, Rev. 5
Freescale Semiconductor 369
19.4.4.3.8 Inside Range, A
≤
address
≤
B
In the Inside Range trigger mode, if the match condition for A and B happen on the same bus cycle, both
the AF and BF flags in the DBGS register are set. If a match condition on only A or only B occur no flags
are set.
19.4.4.3.9 Outside Range, address < A or address > B
In the Outside Range trigger mode, if the match condition for A or B is met, the corresponding flag in the
DBGS register is set.
The four control bits BEGIN and TRGSEL in DBGT, and BRKEN and TAG in DBGC, determine the basic
type of debug run as shown in Table 1.21. Some of the 16 possible combinations are not used (refer to the
notes at the end of the table).
1
When BRKEN = 0, TAG is do not care (x in the table).
2
In end trace configurations (BEGIN = 0) where a CPU breakpoint is enabled (BRKEN = 1), TRGSEL should agree with TAG. In this case, where
TRGSEL = 0 to select no opcode tracking qualification and TAG = 1 to specify a tag-type CPU breakpoint, the CPU breakpoint would not take
effect until sometime after the FIFO stopped storing values. Depending on program loops or interrupts, the delay could be very long.
3
In end trace configurations (BEGIN = 0) where a CPU breakpoint is enabled (BRKEN = 1), TRGSEL should agree with TAG. In this case, where
TRGSEL = 1 to select opcode tracking qualification and TAG = 0 to specify a force-type CPU breakpoint, the CPU breakpoint would erroneously
take effect before the FIFO stopped storing values and the debug run would not complete normally.
4 In begin trace configurations (BEGIN = 1) where a CPU breakpoint is enabled (BRKEN = 1), TAG should not be set to 1. In begin trace debug
runs, the CPU breakpoint corresponds to the FIFO full condition which does not correspond to a taggable instruction fetch.
Table 19-20. Basic Types of Debug Runs
BEGIN TRGSEL BRKEN TAG Type of Debug Run
0 0 0 x
(1)
Fill FIFO until trigger address (No CPU breakpoint - keep
running)
0 0 1 0
Fill FIFO until trigger address, then force CPU breakpoint
0 0 1 1
Do not use
(2)
0 1 0 x
(1)
Fill FIFO until trigger opcode about to execute (No CPU
breakpoint - keep running)
0 1 1 0
Do not use
(3)
0 1 1 1
Fill FIFO until trigger opcode about to execute (trigger causes
CPU breakpoint)
1 0 0 x
(1)
Start FIFO at trigger address (No CPU breakpoint - keep
running)
1 0 1 0
Start FIFO at trigger address, force CPU breakpoint when
FIFO full
1 0 1 1
Do not use
(4)
1 1 0 x
(1)
Start FIFO at trigger opcode (No CPU breakpoint - keep
running)
1 1 1 0
Start FIFO at trigger opcode, force CPU breakpoint when FIFO
full
1 1 1 1
Do not use
(4)