NXP Semiconductors MC9S08LG16, Справочное руководство

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Chapter 6 Parallel Input/Output Control
MC9S08LG32 MCU Series, Rev. 5
116 Freescale Semiconductor
6.7.6 Port F Registers
Port F is controlled by the registers listed below.
6.7.6.1 Port F Data Register (PTFD)
6.7.6.2 Port F Data Direction Register (PTFDD)
7 6 5 4 3 2 1 0
R
PTFD7 PTFD6 PTFD5 PTFD4 PTFD3 PTFD2 PTFD1 PTFD0
W
Reset: 0 0 0 0 0 0 0 0
Figure 6-27. Port F Data Register (PTFD)
Table 6-26. PTFD Register Field Descriptions
Field Description
7:0
PTFD[7:0]
Port F Data Register Bits — For Port F pins that are inputs, reads return the logic level on the pin. For Port F
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For Port F pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTFD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pullups disabled.
7 6 5 4 3 2 1 0
R
PTFDD7 PTFDD6 PTFDD5 PTFDD4 PTFDD3 PTFDD2 PTFDD1 PTFDD0
W
Reset: 0 0 0 0 0 0 0 0
Figure 6-28. Port F Data Direction Register (PTFDD)
Table 6-27. PTFDD Register Field Descriptions
Field Description
7:0
PTFDD[7:0]
Data Direction for Port F Bits — These read/write bits control the direction of Port F pins and what is read for
PTFD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for Port F bit n and PTFD reads return the contents of PTFDn.