NXP Semiconductors MC9S08LG16, Справочное руководство

Страница: 98 / 373

Chapter 6 Parallel Input/Output Control
MC9S08LG32 MCU Series, Rev. 5
98 Freescale Semiconductor
by the shared function. However, the data direction register bit continues to control the source for reads of
the port data register.
When a shared analog function is enabled for a pin, both the input and output buffers are disabled. A value
of 0 is read for any port data bit where the bit is an input (PTxDDn = 0) and the input buffer is disabled. In
general, whenever a pin is shared with both an alternate digital function and an analog function, the analog
function has priority such that if both the digital and analog functions are enabled, the analog function
controls the pin.
It is good programming practice to write to the port data register before changing the direction of a port
pin so it becomes an output. This ensures that the pin is not driven momentarily with an old data value that
happen to be in the port data register.
Figure 6-1. Parallel I/O Block Diagram
6.4 Pullup, Slew Rate, and Drive Strength
Associated with the parallel I/O ports is a set of registers located in the high-page register space that
operates independently of the parallel I/O registers. These registers are used to control pullups, slew rate,
and drive strength for the pins and can be used in conjunction with the peripheral functions on these pins.
6.4.1 Port Internal Pullup Enable
For all GPIOs, set the corresponding bit in the pullup enable register (PTxPEn) to enable an internal pullup
resistor for each port pin. Typically, GPIO internal pullups are disabled when in output mode. However,
for GPIO that are muxed with LCD pins, the internal pullup is not disabled when in open drain, output
mode. Similarly the internal pullup for GPIO muxed with open drain RESET pin is not disabled in the
output mode.
Q D
Q D
1
0
Port Read
PTxDDn
PTxDn
Output Enable
Output Data
Input Data
Synchronizer
Data
BUSCLK
Input Enable