NXP Semiconductors MC9S08LG16, Справочное руководство

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Chapter 13 Timer/Pulse-Width Modulator (S08TPMV3)
MC9S08LG32 MCU Series, Rev. 5
Freescale Semiconductor 317
Reset the TPM counter before writing to the TPM modulo registers to avoid confusion about when the first
counter overflow occurs.
16.3.4 TPM Channel n Status and Control Register (TPMxCnSC)
TPMxCnSC contains the channel-interrupt-status flag and control bits that configure the interrupt enable,
channel configuration, and pin function.
7 6 5 4 3 2 1 0
R CHnF
CHnIE MSnB MSnA ELSnB ELSnA
0 0
W 0
Reset 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 16-12. TPM Channel n Status and Control Register (TPMxCnSC)
Table 16-6. TPMxCnSC Field Descriptions
Field Description
7
CHnF
Channel n flag. When channel n is an input capture channel, this read/write bit is set when an active edge occurs
on the channel n input. When channel n is an output compare or edge-aligned/center-aligned PWM channel,
CHnF is set when the value in the TPM counter registers matches the value in the TPM channel n value registers.
When channel n is an edge-aligned/center-aligned PWM channel and the duty cycle is set to 0% or 100%, CHnF
is not set even when the value in the TPM counter registers matches the value in the TPM channel n value
registers.
A corresponding interrupt is requested when this bit is set and channel n interrupt is enabled (CHnIE = 1). Clear
CHnF by reading TPMxCnSC while this bit is set and then writing a logic 0 to it. If another interrupt request occurs
before the clearing sequence is completed CHnF remains set. This is done so a CHnF interrupt request is not lost
due to clearing a previous CHnF.
Reset clears this bit. Writing a logic 1 to CHnF has no effect.
0 No input capture or output compare event occurred on channel n.
1 Input capture or output compare event on channel n.
6
CHnIE
Channel n interrupt enable. This read/write bit enables interrupts from channel n. Reset clears this bit.
0 Channel n interrupt requests disabled (use for software polling).
1 Channel n interrupt requests enabled.
5
MSnB
Mode select B for TPM channel n. When CPWMS is cleared, setting the MSnB bit configures TPM channel n for
edge-aligned PWM mode. Refer to the summary of channel mode and setup controls in
Table 16-7 .
4
MSnA
Mode select A for TPM channel n. When CPWMS and MSnB are cleared, the MSnA bit configures TPM channel
n for input capture mode or output compare mode. Refer to
Table 16-7 for a summary of channel mode and setup
controls.
Note: If the associated port pin is not stable for at least two bus clock cycles before changing to input capture
mode, it is possible to get an unexpected indication of an edge trigger.
3–2
ELSnB
ELSnA
Edge/level select bits. Depending upon the operating mode for the timer channel as set by CPWMS:MSnB:MSnA
and shown in
Table 16-7 , these bits select the polarity of the input edge that triggers an input capture event, select
the level that is driven in response to an output compare match, or select the polarity of the PWM output.
If ELSnB and ELSnA bits are cleared, the channel pin is not controlled by TPM. This configuration can be used
by software compare only, because it does not require the use of a pin for the channel.