NXP Semiconductors MC9S08LG16, Справочное руководство

Страница: 164 / 373

Chapter 8 LCD Module (S08LCDLPV1)
MC9S08LG32 MCU Series, Rev. 5
164 Freescale Semiconductor
9.3.2 LCD Control Register 1 (LCDC1)
Read: anytime
Write: anytime
Table 9-3. LCDC0 Field Descriptions
Field Description
7
LCDEN
LCD Driver Enable — LCDEN starts LCD-module-waveform generator.
0 All frontplane and backplane pins are disabled. The LCD module system is also disabled, and all LCD
waveform generation clocks are stopped. V
LL3
is connected to V
DD
internally
1 LCD module driver system is enabled and frontplane and backplane waveforms are generated. All LCD pins
enabled using the LCD pin enable register (LCDPEN[x]) will output an LCD module driver waveform.The
backplane pins will output an LCD module driver backplane waveform based on the settings of DUTY[2:0].
Chargepump or resistor bias is enabled.
6
SOURCE
LCD Clock Source Select — The LCD module has two possible clock sources. This bit is used to select which
clock source is the basis for LCDCLK.
0 Selects the OSCOUT (external clock reference) as the LCD clock source.
1 Selects the alternate clock as the LCD clock source.
5:3
LCLK[2:0]
LCD Clock Prescaler — Used as a clock divider to generate the LCD module frame frequency as shown in
Equation 9-1 . LCD-module-duty-cycle configuration is used to determine the LCD module frame frequency. LCD
module frame frequency calculations are provided in Table 9-1 .
Eqn. 9-1
2:0
DUTY[2:0]
LCD Duty Select — DUTY[2:0] bits select the duty cycle of the LCD module driver.
000 Use 1 BP (1/1 duty cycle).
001 Use 2 BP (1/2 duty cycle).
010 Use 3 BP (1/3 duty cycle).
011 Use 4 BP (1/4 duty cycle). (Default)
100 Use 5 BP (1/5 duty cycle).
101 Use 6 BP (1/6 duty cycle).
110 Use 7 BP (1/7 duty cycle).
111 Use 8 BP (1/8 duty cycle).
7 6 5 4 3 2 1 0
R
LCDIEN
0 0 0 0
FCDEN LCDWAI LCDSTP
W
Reset 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 9-4. LCD Control Register 1 (LCDC1)
LCD Module Frame Frequency
((DUTY+1) x 8 x (4 + LCLK[2:0]) x Y)
LCDCLK
=
where 30< LCDCLK
<
39.063 kHz
where Y = 2,2,3,3,4,5,8,16 chosen
by module duty cycle configuration