NXP Semiconductors MC9S08LG16, Справочное руководство

Страница: 320 / 373

Chapter 13 Timer/Pulse-Width Modulator (S08TPMV3)
MC9S08LG32 MCU Series, Rev. 5
320 Freescale Semiconductor
activity depend upon the operating mode, these topics are covered in the associated mode explanation
sections.
16.4.1 Counter
All timer functions are based on the main 16-bit counter (TPMxCNTH:TPMxCNTL). This section
discusses selection of the clock, end-of-count overflow, up-counting vs. up/down counting, and manual
counter reset.
16.4.1.1 Counter Clock Source
The 2-bit field, CLKSB:CLKSA, in the timer status and control register (TPMxSC) disables the TPM
counter or selects one of three clock sources to TPM counter (
Table 16-4 ). After any MCU reset, CLKSB
and CLKSA are cleared so no clock is selected and the TPM counter is disabled (TPM is in a very low
power state). You can read or write these control bits at any time. Disabling the TPM counter by writing
00 to CLKSB:CLKSA bits, does not affect the values in the TPM counter or other registers.
The fixed frequency clock is an alternative clock source for the TPM counter that allows the selection of
a clock other than the bus clock or external clock. This clock input is defined by chip integration. You can
refer chip specific documentation for further information. Due to TPM hardware implementation
limitations, the frequency of the fixed frequency clock must not exceed the bus clock frequency. The fixed
frequency clock has no limitations for low frequency operation.
The external clock passes through a synchronizer clocked by the bus clock to assure that counter
transitions are properly aligned to bus clock transitions.Therefore, in order to meet Nyquist criteria
considering also jitter, the frequency of the external clock source must not exceed 1/4 of the bus clock
frequency.
When the external clock source is shared with a TPM channel pin, this pin must not be used in input
capture mode. However, this channel can be used in output compare mode with ELSnB:ELSnA = 0:0 for
software timing functions. In this case, the channel output is disabled, but the channel match events
continue to set the appropriate flag.
16.4.1.2 Counter Overflow and Modulo Reset
An interrupt flag and enable are associated with the 16-bit main counter. The flag (TOF) is a
software-accessible indication that the timer counter has overflowed. The enable signal selects between
software polling (TOIE = 0) where no interrupt is generated, or interrupt-driven operation (TOIE = 1)
where the interrupt is generated whenever the TOF is set.
The conditions causing TOF to become set depend on whether the TPM is configured for center-aligned
PWM (CPWMS = 1). If CPWMS is cleared and there is no modulus limit, the 16-bit timer counter counts
from 0x0000 through 0xFFFF and overflows to 0x0000 on the next counting clock. TOF is set at the
transition from 0xFFFF to 0x0000. When a modulus limit is set, TOF is set at the transition from the value
set in the modulus register to 0x0000. When the TPM is in center-aligned PWM mode (CPWMS = 1), the
TOF flag is set as the counter changes direction at the end of the count value set in the modulus register
(at the transition from the value set in the modulus register to the next lower count value). This corresponds
to the end of a PWM period (the 0x0000 count value corresponds to the center of a period).