NXP Semiconductors MC9S08LG16, Справочное руководство

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Chapter 13 Timer/Pulse-Width Modulator (S08TPMV3)
MC9S08LG32 MCU Series, Rev. 5
314 Freescale Semiconductor
16.3 Register Definition
16.3.1 TPM Status and Control Register (TPMxSC)
TPMxSC contains the overflow status flag and control bits used to configure the interrupt enable, TPM
configuration, clock source, and prescale factor. These controls relate to all channels within this timer
module.
7 6 5 4 3 2 1 0
R TOF
TOIE CPWMS CLKSB CLKSA PS2 PS1 PS0
W 0
Reset 0 0 0 0 0 0 0 0
Figure 16-7. TPM Status and Control Register (TPMxSC)
Table 16-3. TPMxSC Field Descriptions
Field Description
7
TOF
Timer overflow flag. This read/write flag is set when the TPM counter resets to 0x0000 after reaching the modulo
value programmed in the TPM counter modulo registers. Clear TOF by reading the TPM status and control
register when TOF is set and then writing a logic 0 to TOF. If another TPM overflow occurs before the clearing
sequence is completed, the sequence is reset so TOF remains set after the clear sequence was completed for
the earlier TOF. This is done so a TOF interrupt request cannot be lost during the clearing sequence for a previous
TOF. Reset clears TOF. Writing a logic 1 to TOF has no effect.
0 TPM counter has not reached modulo value or overflow.
1 TPM counter has overflowed.
6
TOIE
Timer overflow interrupt enable. This read/write bit enables TPM overflow interrupts. If TOIE is set, an interrupt is
generated when TOF equals one. Reset clears TOIE.
0 TOF interrupts inhibited (use for software polling).
1 TOF interrupts enabled.
5
CPWMS
Center-aligned PWM select. This read/write bit selects CPWM operating mode. By default, the TPM operates in
up-counting mode for input capture, output compare, and edge-aligned PWM functions. Setting CPWMS
reconfigures the TPM to operate in up/down counting mode for CPWM functions. Reset clears CPWMS.
0 All channels operate as input capture, output compare, or edge-aligned PWM mode as selected by the
MSnB:MSnA control bits in each channel’s status and control register.
1 All channels operate in center-aligned PWM mode.
4–3
CLKS[B:A]
Clock source selection bits. As shown in Table 16-4 , this 2-bit field is used to disable the TPM counter or select
one of three clock sources to TPM counter and counter prescaler.
2–0
PS[2:0]
Prescale factor select. This 3-bit field selects one of eight division factors for the TPM clock as shown in
Table 16-5 . This prescaler is located after any clock synchronization or clock selection so it affects the clock
selected to drive the TPM counter. The new prescale factor affects the selected clock on the next bus clock cycle
after the new value is updated into the register bits.
Table 16-4. TPM Clock Selection
CLKSB:CLKSA TPM Clock to Prescaler Input
00 No clock selected (TPM counter disable)
01 Bus clock