NXP Semiconductors MC9S08LG16, Справочное руководство

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Chapter 6 Parallel Input/Output Control
MC9S08LG32 MCU Series, Rev. 5
Freescale Semiconductor 119
6.7.7 Port G Registers
Port G is controlled by the registers listed below. All Port G pins are shared with LCD. These pins have
special behavior as explained in
Section 6.2 .
6.7.7.1 Port G Data Register (PTGD)
6.7.7.2 Port G Data Direction Register (PTGDD)
7 6 5 4 3 2 1 0
R
PTGD7 PTGD6 PTGD5 PTGD4 PTGD3 PTGD2 PTGD1 PTGD0
W
Reset: 0 0 0 0 0 0 0 0
Figure 6-32. Port G Data Register (PTGD)
Table 6-31. PTGD Register Field Descriptions
Field Description
7:0
PTGD[7:0]
Port G Data Register Bits — For Port G pins that are inputs, reads return the logic level on the pin. For Port G
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For Port G pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTGD to all 0s, but these 0s are not driven out the corresponding pins because reset also
configures all port pins as high-impedance inputs with pullups disabled.
7 6 5 4 3 2 1 0
R
PTGDD7 PTGDD6 PTGDD5 PTGDD4 PTGDD3 PTGDD2 PTGDD1 PTGDD0
W
Reset: 0 0 0 0 0 0 0 0
Figure 6-33. Port G Data Direction Register (PTGDD)
Table 6-32. PTGDD Register Field Descriptions
Field Description
7:0
PTGDD[7:0]
Data Direction for Port G Bits — These read/write bits control the direction of Port G pins and what is read for
PTGD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for Port G bit n and PTGD reads return the contents of PTGDn.