NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
FXTH87ERM
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Reference manual
Rev. 5.0 — 4 February 2019
126 / 183
14.17.4 LFR control register 4 (LFCTL4)
LFCTL4 contains local interrupt enable control bits. The provided I-interrupts are not
globally masked by the I bit in the CPU’s CCR, setting one or more of these interrupt
enable control bits will cause a CPU interrupt to be requested whenever the flag bit
associated with the corresponding LFR interrupt source becomes set. It is good practice
to clear any flag bits in the LFS register before setting interrupt enable bits in this register
in order to avoid an immediate interrupt request.
Table 112. LFR control register 4 (LFCTL4) (address $0023)
Bit
7
6
5
4
3
2
1
0
R
W
LFDRIE
LFERIE
LFCDIE
LFIDIE
DECEN
VALEN
TIMOUT[1:0]
Reset
0
0
0
0
1
1
0
0
Table 113. LFCTL4 register field descriptions
Field
Description
7
LFDRIE
LFR Data Register Full Interrupt Enable — This read/write bit enables interrupts to be requested when the
LFR data register is full. Reset clears LFDRIE.
0 LFDRF interrupts disabled. Use software polling.
1 LFR Data Register Full interrupts are enabled. If LFDRIE is set, then an interrupt is requested when
LFDRF = 1.
6
LFERIE
LFR Error Interrupt Enable — This read/write bit enables interrupts to be requested when the LFR detects
an error in reception of a non-Manchester encoded bit time following the SYNC time. Reset clears LFERIE.
0 LFERF interrupts disabled. Use software polling.
1 LFERF interrupts are enabled. If LFERIE is set, then an interrupt is requested when LFERF = 1.
5
LFCDIE
LFR Carrier Detect Interrupt Enable — This read/write bit enables the LFCDF interrupt when the LFR
detects the number of samples with an LF signal defined by the LFCDTM bits in the LFCTL3 register. The
LFCDIE is ignored when the LFR is operating in the data mode (CARMOD = 0), except when DECEN is
cleared. Reset clears LFCDIE.
0 LFCDF interrupts disabled.
1 LFR LFCDF interrupts are enabled. If LFCDIE is set, then an interrupt is requested when LFCDF = 1.
4
LFIDIE
LFR ID Detect Interrupt Enable — This read/write bit enables interrupts to be requested when the LFR
detects a match to the ID code selected in the LFIDH:L registers. Reset clears LFIDIE.
0 LFIDF interrupts disabled.
1 LFIDF interrupts are enabled. If LFIDIE is set, then an interrupt is requested when LFIDF = 1.
3
DECEN
LF Digital Decode Enable — This read/write bit enables the data processing by the digital decoder. When
disabled, the frame format (Manchester, data-rate, SYNC, data) is not checked. There is no more error flag
assertion (data, error, ID). The MCU should then poll the LFDO bit to extract from the analog detector the bit
stream. Reset sets the DECEN bit.
0 Digital decoder is disabled.
1 Digital decoder is enabled.
2
VALEN
LF Validation Enable — This read/write bit enables the carrier validation process. Reset sets this bit.
0 Carrier Validation disabled.
1 Carrier Validation enabled.
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