NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
FXTH87ERM
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Reference manual
Rev. 5.0 — 4 February 2019
131 / 183
Field
Description
2
ONMODE
ON Behavior Mode — This read/write bit selects how an error will affect the ON time. This bit is cleared by
reset.
0 Any error will stop the ON time.
1 If remaining ON time, the LFR will go back to sniff mode at any error — recommended setting.
1-0
CHK125[1:0]
Accurate 125 kHz Check — The bit controls the CARVAL frequency check method.
00 CARVAL validates on n (2*32 μs packets), n depending on LFCDTM value — recommended setting for
Low Sensitivity mode.
01 Same as 10.
10 CARVAL validates on n (8*8 μs packet), n depending on LFCDTM value — recommended setting for
High Sensitivity mode.
11 Same as 00.
Note:
Setting CHK125[1:0] to either 0x01 or 0x10 increases the immunity to noise and
therefore carries the side effect of narrowing the 125 kHz carrier bandwidth tolerance.
14.17.9 LFR control register C (LFCTRLC, LPAGE = 1)
The LFCTRLC register contains control bits for the LF detector and decoder. It is only
accessible when the LPAGE bit is set.
Table 125. LFR control register C (LFCTRLC, LPAGE = 1) (address $0023)
Bit
7
6
5
4
3
2
1
0
R
W
AMPGAIN[1:0]
FINSEL[1:0]
AZEN
LOWQ[1:0]
DEQEN
Reset
1
1
0
0
1
0
0
0
Table 126. LFCTRLC register field descriptions
Field
Description
7-6
AMPG
AIN[1:0]
3rd Amplifier gain — These bits controls the 3rd amplifier gain.
00 Gain of 2 — recommended setting
01 Gain of 3
10 Gain of 4
11 Gain of 6
5-4
FINSEL[1:0]
Final stage select — These bits select the final stage of the LOGAMP.
00 Continuous time biasing — Fixed Gain 6
01 Continuous time biasing — Programmable Gain — recommended setting
10 4th rectifier disabled
11 4th rectifier disabled
3
AZEN
Data AZ enable — This bit allows the AZ sequence during data frame.
0 AZ during data disabled
1 AZ during data enabled — recommended setting
2-1
LOWQ[1:0]
DeQing Resistor — These bits select the resistor added in parallel to the input network.
00 4 kΩ
01 2 kΩ
10 1 kΩ
11 500 Ω
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