NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
FXTH87ERM
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Reference manual
Rev. 5.0 — 4 February 2019
94 / 183
the main 16-bit counter in the TPM1. Each TPM1 channel is optionally associated with an
MCU pin and a maskable interrupt function.
The TPM1 has center-aligned PWM capabilities controlled by the CPWMS control bit in
TPM1SC. When CPWMS is set to 1, timer counter TPM1CNT changes to an up-/down-
counter and all channels in the associated TPM1 act as center-aligned PWM channels.
When CPWMS = 0, each channel can independently be configured to operate in input
capture, output compare, or buffered edge-aligned PWM mode.
The following sections describe the main 16-bit counter and each of the timer operating
modes (input capture, output compare, edge-aligned PWM, and center-aligned PWM).
Because details of pin operation and interrupt activity depend on the operating mode,
these topics are covered in the associated mode sections.
11.5.1 Counter
All timer functions are based on the main 16-bit counter (TPM1CNTH:TPM1CNTL). This
section discusses selection of the clock source, up-counting vs. up-/down-counting, end-
of-count overflow, and manual counter reset.
After any MCU reset, CLKSB:CLKSA = 0:0 so no clock source is selected and the TPM1
is inactive. Normally, CLKSB:CLKSA would be set to 0:1 so the bus clock drives the
timer counter. The clock source for the TPM1 can be selected to be off, the bus clock
(BUSCLK), the fixed system clock (XCLK), or an external input. The maximum frequency
allowed for the external clock option is one-fourth the bus rate. Refer to
Section 11.4.1
"Timer status and control register (TPM1SC)"
and
Table 87
for more information about
clock source selection.
When the microcontroller is in ACTIVE BACKGROUND mode, the TPM1 temporarily
suspends all counting until the microcontroller returns to normal user operating mode.
During STOP mode, all TPM1 clocks are stopped; therefore, the TPM1 is effectively
disabled until clocks resume. During WAIT mode, the TPM1 continues to operate
normally.
The main 16-bit counter has two counting modes. When center-aligned PWM is selected
(CPWMS = 1), the counter operates in up-/down-counting mode. Otherwise, the counter
operates as a simple up-counter. As an up-counter, the main 16-bit counter counts from
0x0000 through its terminal count and then continues with 0x0000. The terminal count is
0xFFFF or a modulus value in TPM1MODH:TPM1MODL.
When center-aligned PWM operation is specified, the counter counts upward from
0x0000 through its terminal count and then counts downward to 0x0000 where
it returns to up-counting. Both 0x0000 and the terminal count value (value in
TPM1MODH:TPM1MODL) are normal length counts (one timer clock period long).
An interrupt flag and enable are associated with the main 16-bit counter. The timer
overflow flag (TOF) is a software-accessible indication that the timer counter has
overflowed. The enable signal selects between software polling (TOIE = 0) where no
hardware interrupt is generated, or interrupt-driven operation (TOIE = 1) where a static
hardware interrupt is automatically generated whenever the TOF flag is 1.
The conditions that cause TOF to become set depend on the counting mode (up or
up/down). In up-counting mode, the main 16- bit counter counts from 0x0000 through
0xFFFF and overflows to 0x0000 on the next counting clock. TOF becomes set at the
transition from 0xFFFF to 0x0000. When a modulus limit is set, TOF becomes set at the
transition from the value set in the modulus register to 0x0000. When the main 16-bit
counter is operating in up-/down-counting mode, the TOF flag gets set as the counter
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