NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
FXTH87ERM
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Reference manual
Rev. 5.0 — 4 February 2019
46 / 183
7.11.2 System Options Register 1 (SIMOPT1)
The following clock source and frequency selections are available using the system
option register 1 as shown in
Table 39
.
Table 39. System option register 1 (SIMOPT1) (address $1802)
Bit
7
6
5
4
3
2
1
0
R
W
COPE
COPCLKS
STOPE
RFEN
TRE
TRH
BKGDPE
Reset
1
0
0
—
0
0
1
0
= Reserved
Table 40. SIMOPT1 register field descriptions
Field
Description
7
COPE
COP Enable — This control bit enables the COP watchdog. This bit is a write-once bit so that only the first
write after reset is honored. Reset sets the COPE bit.
0 COP Watchdog disabled.
1 COP Watchdog enabled.
6
COPCLKS
COP Clock Select — This control bit selects the clock source for the COP watchdog timer. This bit is a
write-once bit so that only the first write after reset is honored. This bit is cleared by an MCU reset.
0 Select the LFO oscillator output.
1 Select the CPU bus clock.
5
STOPE
STOP Mode Select — This control bit enables/disables the STOP instruction to enter a STOP mode defined
by the SPMSCR2 register. This bit is a write-once bit so that only the first write after reset is honored. This
bit is cleared by an MCU reset.
0 Disable STOP modes.
1 Enable STOP modes.
4
RFEN
RF Module Enable — This bit enables or disables the RF module. This bit is not affected by any reset or
power on after STOP exit. It is only initialized at the first power up. This bit can be written anytime.
1 RF module enabled.
0 RF module disabled.
3
TRE
Temperature Restart Enable — This control bit enables the temperature restart circuit to interrupt the MCU
after being shutdown at either a very high or very low temperature. This bit is cleared by an MCU reset.
0 Temperature restart disabled.
1 Temperature restart enabled.
2
TRH
Temperature Restart Level — This control bit selects whether the temperature restart circuit will interrupt the
MCU after being shutdown on returning from either a very high or very low temperature. This bit is cleared
by an MCU reset.
0 Temperature restart interrupts MCU on return from a very low temperature.
1 Temperature restart interrupts MCU on return from a very high temperature.
1
BKGDPE
BKGD Pin Enable — BKGDPE can be used to allow the BKGD/PTA4 pin to be shared in applications as an
output-only general purpose I/O pin:
0 BKGD function disabled, PTA4 output-only enabled.
1 BKGD function enabled, PTA4 disabled.
0
Reserved
Reserved
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