NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
FXTH87ERM
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Reference manual
Rev. 5.0 — 4 February 2019
31 / 183
6.9.1 FLASH clock divider register (FCDIV)
Bit 7 of this register is a read-only status flag. Bits 6 through 0 can be read at any time
but can be written only once. Before any erase or programming operations are possible,
write to this register to set the frequency of the clock for the nonvolatile memory system
within acceptable limits.
Table 14. FLASH clock divider register (FCDIV) (address $1820)
Bit
7
6
5
4
3
2
1
0
R
W
PRDIV8
DIV5
DIV4
DIV3
DIV2
DIV1
DIV0
Reset
0
0
0
0
0
0
0
0
= Reserved
Table 15. FCDIV register field descriptions
Field
Description
7
DIVLD
Divisor Loaded Status Flag — When set, this read-only status flag indicates that the FCDIV register has
been written since reset. Reset clears this bit and the first write to this register causes this bit to become
set regardless of the data written.
0 FCDIV has not been written since reset; erase and program operations disabled for FLASH
1 FCDIV has been written since reset; erase and program operations enabled for FLASH
6
PRDIV8
Prescale (Divide) FLASH Clock by 8
0 Clock input to the FLASH clock divider is the bus rate clock
1 Clock input to the FLASH clock divider is the bus rate clock divided by 8
5:0
DIV[5:0]
Divisor for FLASH Clock Divider — The FLASH clock divider divides the bus rate clock (or the bus
rate clock divided by 8 if PRDIV8 = 1) by the value in the 6-bit DIV5:DIV0 field plus one. The resulting
frequency of the internal FLASH clock must fall within the range of 200 kHz to 150 kHz for proper FLASH
operations. Program/Erase timing pulses are one cycle of this internal FLASH clock which corresponds to
a range of 5 μs to 6.7 μs. The automated programming logic uses an integer number of these pulses to
complete an erase or program operation.
•
if PRDIV8 = 0 — f
FCLK
= f
BUS
÷ ([DIV5:DIV0] + 1)
•
if PRDIV8 = 1 — f
FCLK
= f
BUS
÷ (8 × ([DIV5:DIV0] + 1))
Table 16
shows the appropriate values for PRDIV8 and DIV5:DIV0 for selected bus frequencies.
Table 16. FLASH clock divider settings
f
BUS
PRDIV8
(Binary)
DIV5:DIV0
(Decimal)
f
FCLK
Program/Erase Timing Pulse
(5 μs Min, 6.7 μs Max)
20 MHz
1
12
192.3 kHz
5.2 μs
10 MHz
0
49
200 kHz
5 μs
8 MHz
0
39
200 kHz
5 μs
4 MHz
0
19
200 kHz
5 μs
2 MHz
0
9
200 kHz
5 μs
1 MHz
0
4
200 kHz
5 μs
200 kHz
0
0
200 kHz
5 μs
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