NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
FXTH87ERM
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© NXP B.V. 2019. All rights reserved.
Reference manual
Rev. 5.0 — 4 February 2019
92 / 183
= Reserved
Table 92. TPM1C1SC register field descriptions
Field
Description
7
CH1F
Channel 1 Flag — When channel n is configured for input capture, this flag bit is set when an active edge
occurs on the channel n pin. When channel 1 is an output compare or edge-aligned PWM channel, CH1F is
set when the value in the TPM1 counter registers matches the value in the TPM1 channel 1 value registers.
This flag is seldom used with center-aligned PWMs because it is set every time the counter matches the
channel value register, which correspond to both edges of the active duty cycle period.
A corresponding interrupt is requested when CH1F is set and interrupts are enabled (CH1IE = 1). Clear
CH1F by reading TPM1C1SC while CH1F is set and then writing a 0 to CH1F. If another interrupt request
occurs before the clearing sequence is complete, the sequence is reset so CH1F would remain set after the
clear sequence was completed for the earlier CH1F. This is done so a CH1F interrupt request cannot be
lost by clearing a previous CH1F. Reset clears CH1F. Writing a 1 to CH1F has no effect.
0 No input capture or output compare event occurred on channel 1
1 Input capture or output compare event occurred on channel 1
6
CH1IE
Channel 1 Interrupt Enable — This read/write bit enables interrupts from channel 1. Reset clears CH1IE.
0 Channel 1 interrupt requests disabled (use software polling)
1 Channel 1 interrupt requests enabled
5
MS1B
Mode Select B for TPM1 Channel 1 — When CPWMS = 0, MS1B = 1 configures TPM1 channel 1 for edge-
aligned PWM mode. For a summary of channel mode and setup controls, refer to
Table 88
.
4
MS1A
Mode Select A for TPM1 Channel 1 — When CPWMS = 0 and MS1B = 0, MS1A configures TPM1 channel
1 for input capture mode or output compare mode. Refer to
Table 88
for a summary of channel mode and
setup controls.
3:2
ELS1[B:A]
Edge/Level Select Bits — Depending on the operating mode for the timer channel as set by
CPWMS:MS1B:MS1A and shown in
Table 88
, these bits select the polarity of the input edge that triggers
an input capture event, select the level that will be driven in response to an output compare match, or select
the polarity of the PWM output.
Setting ELS1B:ELS1A to 0:0 configures the related timer pin as a general-purpose I/O pin unrelated to any
timer channel functions. This function is typically used to temporarily disable an input capture channel or to
make the timer pin available as a general-purpose I/O pin when the associated timer channel is set up as a
software timer that does not require the use of a pin.
Table 93. Mode, edge, and level selection
CPWMS
MS1B:MS1A
ELS1B:ELS1A
Mode
Configuration
X
XX
00
Pin not used for TPM1 channel; use as an external clock for the
TPM1 or revert to general-purpose I/O
01
Capture on rising edge only
10
capture on falling edge only
00
11
Input capture
capture on rising or falling edge
00
software compare only
01
toggle output on compare
10
Clear output on compare
0
01
11
output compare
set output on compare
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