843
Chapter 18
AFCAN Controller
User’s Manual U16580EE3V1UD00
Figure 18-38:
Message buffer redefinition
Notes: 1.
Confirm that a message is being received because RDY bit must be set after a message is
completely received.
2.
Avoid message buffer redefinition during store operation of message reception by waiting
additional 4 CAN data bits.
<~Reference>Figure 18-39 shows the processing for a transmit message buffer during transmission
(MT[2:0] bits of CnMCONFm register = 000B).
START
Set
message buffers
END
RDY = 1?
No
Yes
Clear RDY bit
RDY = 0?
RSTAT = 0 or
VALID = 1?
Note1
No
Clear VALID bit
Set RDY bit
Yes
Yes
No
Wait for 4 CAN data bits
Note2
START
Set
message buffers
END
RDY = 1?
No
Yes
Clear RDY bit
RDY = 0?
RSTAT = 0 or
VALID = 1?
Note1
No
Clear VALID bit
Set RDY bit
Yes
Yes
No
Wait for 4 CAN data bits
Note2
Содержание V850E/PH2
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Страница 192: ...192 Chapter 5 Memory Access Control Function PD70F3187 only User s Manual U16580EE3V1UD00 MEMO...
Страница 312: ...312 Chapter 9 16 Bit Timer Event Counter P User s Manual U16580EE3V1UD00 MEMO...
Страница 534: ...534 Chapter 11 16 bit Timer Event Counter T User s Manual U16580EE3V1UD00...
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Страница 976: ...976 Chapter 22 Internal RAM Parity Check Function User s Manual U16580EE3V1UD00 MEMO...
Страница 984: ...984 Chapter 23 On Chip Debug Function OCD User s Manual U16580EE3V1UD00 MEMO...
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Страница 1036: ...1036 Chapter 27 Recommended Soldering Conditions User s Manual U16580EE3V1UD00 MEMO...
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