553
Chapter 12
16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose Timer (TMENC10)
User’s Manual U16580EE3V1UD00
(6)
Status register 10 (STATUS10)
The STATUS10 register indicates the operating status of TMENC10.
This register is read-only in 8-bit or 1-bit units.
Reset input clears this register to 00H.
Caution:
Overwriting the STATUS10 register during TMENC10 operation (TM1CE bit = 1) is pro-
hibited.
Figure 12-12:
Status Register 10 (STATUS10)
After reset:
00H
R/W
Address:
FFFFF6BFH
7
6
5
4
3
2
1
0
STATUS10
0
0
0
0
0
TM1UDF
TM1OVF
TM1UBD
TM1UDF
TMENC10 Underflow Flag
0
No TMENC10 count underflow
1
TMENC10 count underflow
The TM1UDF bit is cleared (0) upon completion of read access to the STATUS10 register
from the CPU.
TM1OVF
TMENC10 Overflow Flag
0
No TMENC10 count overflow
1
TMENC10 count overflow
The TM1OVF bit is cleared (0) upon completion of read access to the STATUS10 register
from the CPU.
TM1UBD
TMENC10 Up/Down Counter Operation Status
0
TMENC10 up count in progress
1
TMENC10 down count in progress
The state of the TM1UBD bit differs according to the mode as follows.
•
The TM1UBD bit is fixed to 0 when the CMD bit of the TUM10 register = 0 (general-
purpose timer mode).
•
The TM1UBD bit indicates the TMENC10 up/down count status when the CMD bit of
the TUM register = 1 (UDC mode)
Содержание V850E/PH2
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