496
Chapter 11
16-bit Timer/Event Counter T
User’s Manual U16580EE3V1UD00
Figure 11-23:
Basic Operation Flow in External Trigger Pulse Output Mode
Note:
The counter is not cleared upon a match between the counter and the TTnCCR1 buffer register.
Remark:
n = 0, 1
START
Match between counter and
TTnCCR1
External trigger (TTRGTn pin) input
Counter starts counting.
ITTTnCC0
occurrence
Counter clear & start
Initial settings
Timer operation enable (TTnCE = 1)
Transfer of values of TTnCCR0
and TTnCCR1 to buffers TTnCCR0
and TTnCCR1
Match between counter and
TTnCCR0, counter clear & start
External trigger
(TTRGTn pin) input
Clock selection
(TTnCTL1: TTnEEE = 0)
(TTnCTL0: TTnCKS2 to TTnCKS0)
External trigger pulse output mode
setting
(TTnCTL1: TTnMD3 to TTnMD0 = 0010)
Compare register setting
(TTnCCR0, TTnCCR1)
ITTTnCC1
occurrence
Note
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Содержание V850E/PH2
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