CHAPTER 15 SERIAL INTERFACE CSI10
Preliminary User’s Manual U16315EJ1V0UD
317
(b) Serial clock selection register 10 (CSIC10)
CSIC10 can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Address: FF81H After reset: 00H R/W
Symbol
7
6
5
4
3
2
1
0
CSIC10
0
0
0
CKP10
DAP10
CKS102
CKS101
CKS100
CKP10
DAP10
Data clock phase selection
Type
0
0
D7
D6
D5
D4
D3
D2
D1
D0
SCK10
SO10
SI10 input timing
1
0
1
D7
D6
D5
D4
D3
D2
D1
D0
SCK10
SO10
SI10 input timing
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
SCK10
SO10
SI10 input timing
3
1
1
D7
D6
D5
D4
D3
D2
D1
D0
SCK10
SO10
SI10 input timing
4
CKS102
CKS101
CKS100
CSI10 count clock selection
0
0
0
f
X
/2 (5 MHz)
0
0
1
f
X
/2
2
(2.5 MHz)
0
1
0
f
X
/2
3
(1.25 MHz)
0
1
1
f
X
/2
4
(625 kHz)
1
0
0
f
X
/2
5
(312.5 kHz)
1
0
1
f
X
/2
6
(156.25 kHz)
1
1
0
f
X
/2
7
(78.13 kHz)
1
1
1
External clock input to SCK10
Cautions 1. Do not write CSIC10 during a communication operation or when using P10/SCK10/T
X
D0,
P11/SI10/R
X
D0, and P12/SO10 as general-purpose port pins.
2. The phase type of the data clock is type 1 after reset.
Remarks 1.
Figures in parentheses are for operation with f
X
= 10 MHz
2.
f
X
: X1 input clock oscillation frequency
Содержание 78K0/KD1 Series
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