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CHAPTER 12 A/D CONVERTER
Preliminary User’s Manual U16315EJ1V0UD
231
(3) Power-fail comparison mode register (PFM)
The power-fail comparison mode register (PFM) is a register that controls the comparison operation.
PFM can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Figure 12-7. Format of Power-Fail Comparison Mode Register (PFM)
0
0
0
0
0
0
PFCM
PFEN
Power-fail comparison enable
Stops power-fail comparison (used as a normal A/D converter)
Enables power-fail comparison (used for power-fail detection)
PFEN
0
1
Power-fail comparison mode selection
Interrupt request signal (INTAD) generation
No INTAD generation
No INTAD generation
INTAD generation
ADCR3
≥
PFT3
ADCR3 < PFT3
ADCR3
≥
PFT3
ADCR3 < PFT3
PFCM
0
1
0
1
2
3
4
5
6
7
PFM
Address: FF2AH After reset: 00H R/W
Symbol
Caution
If data is written to PFM, a wait cycle is generated. Do not write data to PFM when the CPU is
operating on the subsystem clock and the X1 input clock is stopped. For details, refer to
CHAPTER 29 CAUTIONS FOR WAIT.
(4) Power-fail comparison threshold register (PFT)
The power-fail comparison threshold register (PFT) is a register that sets the threshold value when comparing the
values with the A/D conversion result.
8-bit data in PFT is compared to the higher 8 bits (FF09H) of the 10-bit A/D conversion result.
PFT can be set by an 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Figure 12-8. Format of Power-Fail Comparison Threshold Register (PFT)
PFT0
PFT1
PFT2
PFT3
PFT4
PFT5
PFT6
PFT7
0
1
2
3
4
5
6
7
PFT
Address: FF2BH After reset: 00H R/W
Symbol
Caution
If data is written to PFT, a wait cycle is generated. Do not write data to PFT when the CPU is
operating on the subsystem clock and the X1 input clock is stopped. For details, refer to
CHAPTER 29 CAUTIONS FOR WAIT.
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