CHAPTER 5 CLOCK GENERATOR
Preliminary User’s Manual U16315EJ1V0UD
104
5.2 Configuration of Clock Generator
The clock generator consists of the following hardware.
Table 5-1. Configuration of Clock Generator
Item
Configuration
Control registers
Processor clock control register (PCC)
Ring-OSC mode register (RCM)
Main clock mode register (MCM)
Main OSC control register (MOC)
Oscillation stabilization time counter status register (OSTC)
Oscillation stabilization time select register (OSTS)
Oscillator
X1 oscillator
Ring-OSC oscillator
Subsystem clock oscillator
Figure 5-1. Block Diagram of Clock Generator
X1
X2
f
XP
f
XT
FRC
XT1
XT2
f
X
2
2
STOP
MSTOP
f
X
2
3
f
X
2
4
f
X
2
4
RSTOP
CSS PCC2
CLS
MCM0
MCS
CLS
MCC
OSTS1 OSTS0
OSTS2
1/2
3
MOST
16
MOST
15
MOST
14
MOST
13
MOST
11
C
P
U
f
R
f
X
PCC1 PCC0
X1 oscillator
Internal bus
Ring-OSC mode
register (RCM)
Main OSC
control
register
(MOC)
Internal bus
Ring-OSC
oscillator
Mask option
1: Cannot be stopped
0. Can be stopped
CPU clock
(f
CPU
)
Controller
Processor clock
control register
(PCC)
Main clock
mode register
(MCM)
X1 oscillation
stabilization time counter
Oscillation
stabilization time
select register
(OSTS)
Oscillation
stabilization
time counter
status
register
(OSTC)
Clock to peripheral
hardware
Prescaler
Operation
clock switch
8-bit timer H1,
watchdog timer
Prescaler
Prescaler
Selector
Subsystem
clock oscillator
Watch clock,
clock output
function
Содержание 78K0/KD1 Series
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