CHAPTER 5 CLOCK GENERATOR
Preliminary User’s Manual U16315EJ1V0UD
120
Figure 5-13. Status Transition Diagram (4/4)
(4) When “Ring-OSC cannot be stopped” is selected by mask option
(when subsystem clock is used)
HALT
Interrupt
Interrupt
Interrupt
STOP
instruction
MCM0 = 0
MCM0 = 1
Note 1
HALT
instruction
HALT
instruction
STOP
Note 3
Reset
Note 6
Interrupt
STOP
instruction
Interrupt
Interrupt
STOP
instruction
MSTOP = 1
Note 2
MSTOP = 0
HALT instruction
Reset release
MCC = 0
CSS = 0
Note 5
MCC = 1
CSS = 1
Note 4
Interrupt
Interrupt
HALT instruction
HALT instruction
Status 3
CPU clock: f
XP
f
XP
: Oscillating
f
R
: Oscillating
Status 2
CPU clock: f
R
f
XP
: Oscillating
f
R
: Oscillating
Status 1
CPU clock: f
R
f
XP
: Oscillation stopped
f
R
: Oscillating
Status 5
CPU clock: f
XT
f
XP
: Oscillation stopped
f
R
: Oscillating/
oscillation stopped
Status 4
CPU clock: f
XT
f
XP
: Oscillating
f
R
: Oscillating/
oscillation stopped
Notes 1.
Before shifting from status 2 to status 3 after reset and STOP are released, check the X1 input clock
oscillation stabilization time status using the oscillation stabilization time counter status register
(OSTC).
2.
When shifting from status 2 to status 1, make sure that MCS is 0.
3.
The watchdog timer operates using Ring-OSC even in STOP mode if “Ring-OSC cannot be stopped”
is selected by a mask option. Ring-OSC division can be selected as the count source of 8-bit timer
H1 (TMH1), so clear the watchdog timer using the TMH1 interrupt request before watchdog timer
overflow. If this processing is not performed, an internal reset signal is generated at watchdog timer
overflow after STOP instruction execution.
4.
Shifting to status 4 (subsystem clock operation) can be performed only from status 3 (X1 input clock
operation).
5.
Shifting to status 1 or status 2 from status 4 is not possible.
6.
All reset sources (RESET input, POC, LVI, clock monitor, and WDT)
Содержание 78K0/KD1 Series
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