DS3 UNI PORT CONFIGURATION
76-02-031E
100
14. 7 DS3 ATM masks
The DSU deletes cells whose headers match the mask identified by the
IDLE CELLS
entry.
Note that IDLE cells have a CLP bit set to 1 while unassigned cells have this bit set to 0. (By
default, this bit is set to x to delete both cell types. After idle cells have been deleted, cells
that match the good cell mask are forwarded through the switching matrix. This process
filters the good traffic.
The
DS3 ATM MASKS
menu is accessed using the path:
M
AIN SET-UP / ATM MASKS / DS3 PORT
Figure 14.6 DS3 ATM masks
14. 8 DS3 Physical layer error types
Errors within the following primitives may be gathered to generate performance data:
Figure 14.7 DS3 Physical layer error types
DS3 PORT
1 - idle cell GFC
0000
2 - idle cell VPI
00000000
3 - idle cell VCI
0000000000000000
4 - idle cell PT
000
5 - idle cell CLP
X
6 - good cell GFC
XXXX
7 - good cell VPI
XXXXXXXX
8 - good cell VCI
XXXXXXXXXXXXXXXX
9 - good cell PT
XXX
0 - good cell CLP X
Display
Description
LCV
B3ZS Line Code Violation error
Frame errors
Frame alignment word errors
BIP-8
PLCP BIP-8 (parity) errors
FEBE
FEBE’s (Far End Block Errors) giving statistics based upon far end
receiver performance
Содержание ATM CBR DSU
Страница 2: ......
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Страница 10: ......
Страница 16: ...INTRODUCTION 76 02 031E 6...
Страница 20: ...STATUTORY INFORMATION 76 02 031E 10...
Страница 34: ...INSTALLING SETTING UP 76 02 031E 24...
Страница 56: ...CONFIGURING THE ATM CBR DSU 76 02 031E 46...
Страница 78: ...ANALYSING PERFORMANCE 76 02 031E 68...
Страница 88: ...E1 CBR PORT CONFIGURATION 76 02 031E 78...
Страница 92: ...E2 CBR PORT CONFIGURATION 76 02 031E 82...
Страница 96: ...E3 CBR PORT CONFIGURATION 76 02 031E 86...
Страница 100: ...DS3 CBR PORT CONFIGURATION 76 02 031E 90...
Страница 106: ...E3 UNI PORT CONFIGURATION 76 02 031E 96...
Страница 112: ...DS3 UNI PORT CONFIGURATION 76 02 031E 102...
Страница 120: ...SDH Sonet UNI PORT CONFIGURATION 76 02 031E 110...