LSI Logic Confidential
8-8
Host Slave Interface
Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
•
The DMN-8600 processor uses the LOW-to-HIGH edge of CS to
latch in data and to stop driving WAIT (6).
•
The DMN-8600 processor deasserts DTACK, then stops driving
DTACK on the LOW-to-HIGH (7) edge of CS.
Figure 8.4
M-Mode WRITE
8.3.6
M-Mode Outgoing Transfers
shows an M-mode read. The sequence is as follows:
•
The DMN-8600 processor samples the Address and RD/WR (1) on
the HIGH-to-LOW edge of CS.
•
The processor asserts WAIT (2) and deasserts DTACK from a 3-
state to HIGH level (shaded area is 3-state) in response to the
HIGH-to-LOW transition of CS.
•
The DMN-8600 processor deasserts WAIT (3) and asserts DTACK
after driving data out.
•
Deassertion of WAIT or assertion of DTACK causes CS (4) to be
deasserted.
•
The DMN-8600 processor stops driving data and WAIT (5) in
response to the deassertion of CS.
•
The DMN-8600 processor stops driving DTACK and then stops
driving DTACK (6) also in response to the CS deassertion.
CS (I)
WR (I)
WAIT (O)
DTACK (O)
A[2:0] (I)
D[31:0] (I/O)
3
4
3
5
2
1
Address
Data
7
6
4
Содержание DMN-8600
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