LSI DMN-8600, Техническое руководство

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LSI Logic Confidential
18-14 Specifications
Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
18.2.3 Host Slave Timing
The diagrams shown in Figures 18.12 , 18.13 , 18.14 and 18.15 give the
slave mode read-from and write-to timing.
Table 18.6 Async Host Master Timing Parameters - Host Slave and Slave plus Limited
Master Modes Only
Parameters Description Min Max
T
PW
M_ALE pulse width from M_A and M_ALE
asserted to fall of M_ALE. This can be treated
as setup time by external slave. AS clock
cycles
−
2 ns
AS clock cycles
+ 2 ns
T
AH
Time from fall of M_ALE to M_A/M_D change.
This can be treated as hold time by an
external slave. AH clock
cycles
−
4 ns
AH clock cycles
+ 3 ns
T
CS
Delay from M_A to fall of M_CS. CS clock
cycles
−
7 ns
CS clock cycles
+ 2 ns
T
DS
Delay from M_A to fall of data strobes. DS clock
cycles
−
4 ns
DS clock cycles
+ 4 ns
T
data_valid_begin(n)
1
1. The parameters T
data_valid_begin(n)
and T
data_valid_end(n)
represent the minimum possible window dur-
ing which the data pins must be stable.
Delay from M_A and M_RD/WR stable to
stable nth read data (applicable for bursts and
single access). DT + (n-1)
(BDT + 1) clock
cycles
−
6 ns
T
holdCS
Read data hold time with respect to CS rising. 1 clock cycle BH
−
1 clock
cycle
T
data_valid_end(n)
1
Delay for stable address to end of nth read
data during bursts (for single access, T
holdCS
is applicable).
DT + (n
−
1)
(BDT + 1) + 3
clock cycles.
T
write_data_valid
Delay from write strobe falling to write data
valid.
−
DS clock
cycles
−
4 ns
−
DS clock
2 ns
T
write_data_hold
Write data hold time after strobe pulls up BH clock
cycles
−
4 ns
BH clock cycles
+ 2 ns
T
BH
Delay from end of cycle to start of next cycle. BH clock
cycles
−
2 ns